CMOS device structure based on silicon-on-insulator substrate and preparation method thereof

Abstract

The invention provides a CMOS device structure based on a silicon-on-insulator substrate and a preparation method thereof. The CMOS device structure comprises the silicon-on-insulator substrate and a CMOS device. The silicon-on-insulator substrate comprises bottom silicon, an insulating layer and top silicon, and the positions corresponding to preparation of transistor channels of the insulating layer is provided with grooves penetrating through the top silicon and the bottom silicon. The CMOS device is manufactured on the silicon-on-insulator substrate, and the channels of the CMOS device are manufactured in the top silicon corresponding to the grooves. The CMOS device is manufactured on the silicon-on-insulator substrate. The positions corresponding to preparation of the transistor channels of the insulating layer of the silicon-on-insulator substrate are provided with the grooves penetrating through the top silicon and the bottom silicon so as to arrange holes below a CMOS device body region, and thus reliability of the subsequently prepared CMOS device can be greatly increased. The CMOS device structure is simple in structure and method, and reliability of the device can be effectively enhanced so that the CMOS device structure has wide application prospect in the field of semiconductor manufacturing.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, in particular to a method for preparing a CMOS device structure based on a silicon substrate on insulator islands. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, SOI has gradually become a deep submicron low-voltage, low-voltage The mainstream ...

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Problems solved by technology

[0008] First, there is a certain parasitic capacitance between the source drain and the substrate, which affects the device speed;

[0009] Second, the source-drain is coupled through the underlying BOX, which is prone to short-channel effects in smaller-sized devices;

[0010] Third, the defects in the insulating layer below the channel will scatter the channel carriers and affect the mobility of the carriers;

[0011] Fourth, after high-energy particles are incident, electron-hole pairs will be excited in the BOX insulating layer, which will affect the radiation resistance of the device

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