Layout structure design method of standard cell library employing FinFET process

Abstract

The invention provides a layout structure design method of a standard cell library employing an FinFET process. The method comprises the following steps: (1) obtaining admissible values of the distances between fins according to process simulation; (2) defining a wiring distance of a metal layer according to a process design rule and obtaining reference indexes of the heights of cells in the standard cell library; (3) determining the midline position information of the layout structures of the cells by combining the wiring distance; (4) defining admissible values of the widths of regions of the cells in the layout structures through the midline position information, the process design rule and the admissible values of the distances between the fins; and (5) designing the widths of the active regions of the cells in the standard cell library by simulation iteration, thereby optimizing timing parameters of the cells. According to the design method provided by the invention, the optimal value of the distances between the Fins in the layout structures of the cells in the standard cell library is designed through iteration according to the admissible values of the distances between the Fins through the process simulation and the performance requirements of a phase inverter of the standard cell library; and the automatic design efficiency and accuracy of the FinFET are effectively improved.

Description

technical field [0001] The invention relates to a method for designing a structure of a semiconductor device, in particular to a method for designing a layout structure of a FinFET process standard cell library. Background technique [0002] The design of CMOS digital IC can usually be divided into full-custom design and semi-custom design. Full-custom design is a transistor-level based design methodology where all components, interconnects, and layout of a circuit are designed directly. For example, customize its unique aspect ratio and other parameters for each MOSFET, and adjust its specific parasitic distribution parameters by adjusting the polysilicon doping concentration or metal material, width and other parameters of the wiring for each critical path. Full custom design can better improve device performance, but it is time-consuming and it is difficult to fully realize automatic design. Semi-custom designs can be gate array-based or standard cell library-based desi...

AI Technical Summary

Problems solved by technology

[0011] However, due to the continuous shrinking of FinFET devices, the existing standard cell library layout design method suitable for thick body CMOS design is difficult to directly apply to FinFET

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