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A planar non-volatile resistive memory and its preparation method

A resistive memory, non-volatile technology, applied in static memory, digital memory information, information storage and other directions, can solve the problem of not fully meeting the requirements of non-volatile memory development, and achieves reducing the difficulty of preparation and enriching the production. Craftsmanship, the effect of expanding the range

Active Publication Date: 2018-06-12
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In recent years, with the further development of integrated circuits, the requirements for size reduction, power consumption reduction and high integration of non-volatile memory have been continuously improved. Consumption and other restrictions, can not fully meet the requirements of the development of non-volatile memory

Method used

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  • A planar non-volatile resistive memory and its preparation method
  • A planar non-volatile resistive memory and its preparation method
  • A planar non-volatile resistive memory and its preparation method

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Experimental program
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Embodiment 1

[0035] In this embodiment, the spacer structure 2 of the resistive variable layer uses TaOx as the functional layer of the resistive variable memory, and the sacrificial layer adopts polysilicon.

[0036] The preparation method of the planar nonvolatile resistive memory in this embodiment includes the following steps:

[0037] 1) Select the substrate 1 according to the application. For example, a transparent glass substrate can be used to prepare a transparent resistive memory, and a flexible organic material can be used as a substrate to make a flexible memory; A 50nm-1000nm thick polysilicon film is deposited on the substrate 1 as a sacrificial layer.

[0038] 2) Use photolithography to define a pattern on the sacrificial layer, and etch on the sacrificial layer to form a sacrificial layer pattern 03, such as figure 2 shown.

[0039] 3) Deposit a resistive material layer on the sacrificial layer:

[0040]3.1) Prepare a layer of resistive thin film material by PVD reactiv...

Embodiment 2

[0049] In this embodiment, the resistive layer sidewall structure 2 is made of organic material parylene, and the material of the sacrificial layer is made of Si 3 N 4 , to prepare small-scale nano-planar resistive variable memory.

[0050] 1) Deposit Si with a thickness of 50nm to 1000nm on a transparent glass substrate by plasma enhanced chemical vapor deposition method PECVD 3 N 4 film, forming a sacrificial layer.

[0051] 2) Use photolithography to define the sacrificial layer pattern, and use dry etching to form the sacrificial layer pattern 03, such as figure 2 shown.

[0052] 3) On the basis of the above, the first layer of parylene-C (Parylene-C) layer is grown by Polymer CVD; the deposition adopts parylene Polymer CVD equipment, and the standard parameters of the equipment are selected for the process, and the thickness is 20nm. The deposition rate is between 1nm / min and 10nm / min to form a resistive material layer 04, such as image 3 shown.

[0053] 4) Use I...

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Abstract

The invention discloses a planar non-volatile resistive variable memory and a preparation method thereof. In the resistive memory of the present invention, a planar structure of electrode-resistive layer-electrode is formed in the horizontal direction of the substrate; the resistive layer is prepared by using a sidewall structure, and the thickness and width of the sidewall can be controlled to a certain extent through appropriate design ; A resistive variable layer with a small nanoscale horizontal "width" can be realized by using the sidewall plus selective etching process, that is, the gap between two electrodes required for making a planar resistive variable memory. Using this method cleverly avoids the limitations brought by the process and equipment, even if the existing most advanced process is not used, small-scale nanoscale devices can be realized, and the process adopted in the present invention is fully compatible with the CMOS process The manufacturing process expands the scope of its application; the preparation of nano-planar resistive memory is not only of great significance to the research of resistive memory, but also plays an important role in the preparation process of resistive memory in the industry.

Description

technical field [0001] The invention relates to CMOS hybrid integrated circuit technology, in particular to a planar non-volatile resistive variable memory and a preparation method thereof. Background technique [0002] In recent years, with the further development of integrated circuits, the requirements for size reduction, power consumption reduction and high integration of non-volatile memory have been continuously improved. However, due to the limitation of consumption and other aspects, it can no longer fully meet the requirements of the development of non-volatile memory. [0003] Emerging resistive memory has received extensive attention in the field of semiconductor integrated circuits. The advantages of resistive memory in terms of high integration, low power consumption, and read / write speed make it a strong competitor in the new generation of memory. RRAM relies on the reversible state transition between high resistance state ("0" state) and low resistance state ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L45/00H01L27/24G11C13/00
CPCG11C13/00G11C13/0009H10B63/00H10N70/00
Inventor 蔡一茂王宗巍黄如刘业帆潘越余牧溪
Owner PEKING UNIV