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Displayport interface and clock recovery method therefor

A clock recovery and interface technology, used in signal generation/distribution, instruments, electrical digital data processing, etc., can solve the problem that signal clock recovery is difficult to meet requirements, achieve good compatibility and reduce inter-symbol crosstalk.

Active Publication Date: 2016-09-28
BEIJING PICO TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, the clock recovery of signals by embedded processors is difficult to meet the requirements

Method used

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  • Displayport interface and clock recovery method therefor
  • Displayport interface and clock recovery method therefor

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Embodiment Construction

[0036] In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0037] figure 1 It is a flow chart of a method for clock recovery of a Displayport interface provided by an embodiment of the present invention. Such as figure 1 As shown, the method for Displayport interface clock recovery that the embodiment of the present invention provides comprises:

[0038] Step S110: Connect a clock synchronization chip to the embedded processor of the Displayport interface through the IIC bus, so that the embedded processor can control the clock synchronization chip through the IIC bus. The IIC bus is a multi-directional control bus. Multiple chips can be connected to the same bus structure. At the same time, each chip can be used as a control source for real-time data transmission, thus simplifying the signa...

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Abstract

The invention discloses a Displayport interface and a clock recovery method therefor. The method comprises the steps of connecting a clock synchronization chip to an embedded processor of the Displayport interface through an IIC bus so as to enable the embedded processor to control the clock synchronization chip through the IIC bus; connecting an auxiliary transmission channel of a Displayport interface connector to the embedded processor; connecting a main channel and a hot-plugging detection channel of the Displayport interface connector to the clock synchronization chip; and after link training succeeds, recovering a clock signal from a signal of the main channel by utilizing the clock synchronization chip, and synchronously sending the clock signal, the signal of the main channel and a signal of the hot-plugging detection channel to the embedded processor. Therefore, inter-symbol interference is effectively reduced, excellent communication quality is realized, and better compatibility is achieved for devices produced by different manufacturers.

Description

technical field [0001] The invention relates to the technical field of computer hardware, in particular to a Displayport interface and a clock recovery method thereof. Background technique [0002] High-definition digital video has gradually reached 4K or even 8K resolution, which poses new challenges to the physical layer design of video data signal transmission. Compared with the previous generation of video interface protocol HDMI, the Displayport interface uses the clock embedded in the code stream instead of an independent clock signal, thereby further reducing the number of links and improving the physical bandwidth. The sending end uses 8b / 10b encoding to process the signal. At the receiving end, the signal needs to be bit-synchronized to achieve clock recovery. Since the signal rate is as high as 5.4Gbps, it is necessary to eliminate the inter-symbol crosstalk to the greatest extent and ensure the timing requirements of the symbols to achieve excellent communication...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G06F1/12
Inventor 舒玉龙
Owner BEIJING PICO TECH