Virtual-channel low-power circuit applied to network-on-chip

Abstract

The invention discloses a virtual-channel low-power circuit applied to a network-on-chip. The virtual-channel low-power circuit is characterized by comprising a clock anticipation on / off module composed of a clock enabling generation module and a clock gating generation module and a cache segmentation gating module composed of a read-write signal control module and a segmented clock gating module. According to the virtual-channel low-power circuit applied to the network-on-chip, the utilization rate of single virtual-channel cache can be increased, the problems of depending on software monitoring and being tight in timing are avoided, power of input cache in the network-on-chip is reduced, the whole Noc power is reduced, and correct transmission of data is guaranteed.

Description

technical field [0001] The invention belongs to the communication technical field of integrated circuit on-chip network, and in particular relates to a virtual channel low-power design circuit applied to on-chip network. Background technique [0002] With the reduction of the feature size of integrated circuits and the increase of clock frequency, the number of transistors integrated on a single chip exceeds 1 billion orders of magnitude, the interconnection line density continues to increase, and the interconnection architecture accounts for an increasing proportion of the overall power consumption of the chip, thus reducing communication The power consumption of the network is very important; the power consumption of the network on chip mainly comes from the transmission power consumption of the data packet and the storage power consumption; researchers have observed that the energy consumed by storing a data packet is much greater than the energy consumed by transmitting a...

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the situation that the network data injection rate is high, the cache demand is relatively large, and the cache distribution of each node is uneven, the present invention proposes a virtual channel low power consumption circuit applied to the network on chip, in order to improve the single virtual channel cache Utilization, avoid relying on software monitoring and timing issues, thereby reducing the power consumption of the input buffer in the network on chip, thereby reducing the power consumption of the entire NoC, and ensuring the correct transmission of data

Images