Method for simultaneously fabricating semiconductor elements in unit cell region and surrounding region

Abstract

The invention provides a method for simultaneously manufacturing the semiconductor elements of a cell region and a surrounding region. The method comprises the steps of sequentially forming a gate oxide layer, a first conductor structure layer, an inter-gate dielectric layer and a second conductor structure layer on a substrate; forming a mask structure on the second conductor structure layer; adopting the mask structure as an etching mask to remove the second conductor structure layer in the cell region and in the surrounding region; adopting the inter-gate dielectric layer as an etching stop layer; covering the inter-gate dielectric layer in the surrounding region with a protection layer; etching the inter-gate dielectric layer and the first conductor structure layer both exposed out of the cell region; etching the inter-gate dielectric layer and the first conductor structure layer in the surrounding region; and adopting the gate oxide layer as the etching stop layer. According to the technical scheme of the invention, the damage risk of the oxide layer in the surrounding region is reduced.

Description

technical field

[0001] The invention relates to a semiconductor process, in particular to a method for simultaneously manufacturing semiconductor elements in a unit cell region and a surrounding region. Background technique

[0002] With the development of semiconductor components into the nanometer generation, more and more difficulties are faced. For example, with the reduction of line width and increase of line density, there are severe tests in terms of pattern accuracy and process control.

[0003] For example, when fabricating the gate structure, the gate oxide layer is generally used as the etching stop layer. Moreover, the etching process usually first considers whether the device outline conforms to the design, so when the cell area and the surrounding area are fabricated at the same time, the risk of gate oxide layer damage due to over-etching often increases.

[0004] In addition, as the gate length of transistors shrinks, the easiest way to increase circuit spee...

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