Semiconductor device

Abstract

The present invention disclose a semiconductor device which comprises a chip with an active surface and a back surface opposite to the active surface, moulding materials covering the part of the chip except the active surface, a redistribution layer arranged on the active surface and the moulding materials, wherein the redistribution layer is electrically connected with the chip, and a stress buffer structure feature inlaid in the moulding materials.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a wafer-level package (WLP), which has stress-relief features and is arranged on top of a molding compound. Background technique [0002] The wafer level packaging process is well known to those skilled in the art. In the wafer-level packaging process, the wafer on which the integrated circuit is formed or the chip is mounted on will go through a series of processes, such as polishing, die alignment bonding, and molding, and finally cut to obtain the final product. Nowadays, it is generally believed in the field that the wafer level packaging process is the most suitable technology for small-size and high-speed chip packaging. [0003] In the prior art, when WLP is performed, a relatively thick molding compound is used to cover the wafer and the die mounted on the wafer. Since the coefficient of thermal expansion (CTE) of the molding compound is different from that of the wafer...

AI Technical Summary

Problems solved by technology

[0004] Wafer warpage makes it difficult to maintain the connection between the die and the wafer, resulting in the failure of the stacked assembly of the die and the wafer

The warpage problem is more obvious on large-sized wafers, making wafer-level packaging of large-sized wafers more difficult

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