A kind of semiconductor device and its preparation method, electronic device

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method comprises the step of: S1, providing a semiconductor substrate, and forming a plurality of fins on the semiconductor substrate, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, NMOS gates surrounding the fins are formed on the NMOS region, and PMOS gates surrounding the fins are formed on the PMOS region; S2, executing pocket ion implantation on two sides of the NMOS gates; S3, executing LDD ion implantation on two sides of the NMOS gates, so as to form an NMOS LDD region; S4, forming first grooves on two sides of the PMOS gates and carrying out pre-baking; S5, forming a first semiconductor material layer in each first groove through epitaxial growth, and conducting in-situ doping to form PMOS uplift source-drains; S6, and executing an annealing step so that in-situ doped ions diffuse below the PMOS gates to form a PMOS LDD extension area.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits. [0003] As the dimensions of CMOS devices continue to shrink, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, FinFET is an advanced semiconductor devic...

AI Technical Summary

Problems solved by technology

[0004] During the manufacturing process of FinFET devices, the raised source and drain are usually formed on the source and drain regions by epitaxy to introduce stress in the channel, and at the same time reduce the source and drain epitaxial resistance and contact resistance. There are high temperature processes such as H 2 Pre-baking, etc., the temperature can reach 780-850 ° C, at the higher temperature, the loss of pocket implanted ions in FinFET devices will increase, especially for the loss of B ions in PMOS. This increases the epitaxial resistance and degrades the performance of FinFET devices

Due to the continuous shrinking of the size of semiconductor devices, such as narrower fins, this further exacerbates the loss of B ions and the shadow effect of pocket implants.

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