Forming method of semiconductor structure
A semiconductor and transistor technology, applied in the field of semiconductor structure formation, can solve the problems of slow erasing speed and low coupling efficiency, and achieve the effects of increasing uniformity, ensuring uniformity, improving operating speed and coupling efficiency
Active Publication Date: 2017-06-09
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0011] However, the MTP device formed by the prior art has the disadvantages of low coupling efficiency and slow erasing speed
Method used
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Embodiment Construction
[0026] There are many problems in the formation method of the semiconductor structure in the prior art, for example, the erasing speed of the formed storage device is slow.
[0027] Combining with the formation method of the semiconductor structure in the prior art, the reasons for the slow erasing speed of the storage device are analyzed:
[0028] refer to figure 1 and figure 2 , in the prior art, in the step of forming the hard mask layer 102 on the substrate 100, in order to enable the hard mask layer 102 to fully protect the gate layer 101 in the first region I during the process of etching the gate layer 101 , the thickness of the hard mask layer 102 is relatively large.
[0029] Such as Figure 4 As shown, in the process of forming the fourth gate 140 by etching, the hard mask layer 102 above the second gate 120 is reserved as an insulating dielectric layer under the fourth gate 140 .
[0030] In order to ensure that the insulating dielectric layer under the fourth...
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The invention provides a forming method of a semiconductor structure. After a first hard mask layer is formed on a gate layer, the first hard mask layer in a second region is removed, the first hard mask layer in a first region is retained, and a second hard mask layer is formed on the first hard mask layer and on the gate layer in the second region, wherein the thickness of the second hard mask layer is smaller than that of the first hard mask layer. Thus, when the second hard mask layer is not thinned by etching but retained directly as an insulating medium layer under a third gate, the second hard mask layer is not too thick to affect the performance of a memory. In addition, before the first hard mask layer, the second hard mask layer and the gate layer are etched, the second hard mask layer is coated with an antireflection coating. The antireflection coating can protect the second hard mask layer in the second region in the etching process and ensure the uniformity of the second hard mask layer. Therefore, the uniformity of the insulating medium layer under the third gate is increased, and the performance of memory devices is improved.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] The manufacturing process of the multiple programmable (More Time Programming, MTP) memory device can be coupled with the logic circuit, and the cost is low, so it is widely used. The MTP device includes: a storage tube and a control tube, and some multi-time programmable memories also have a selection tube. [0003] Figure 1 to Figure 5 A structural schematic diagram showing various steps in a method for forming a semiconductor structure in the prior art. [0004] Please refer to figure 1 , a substrate 100 is provided, and the substrate 100 includes a first region I for forming a logic device and a second region II for forming a storage device. continue to refer figure 1 , forming a first gate layer 101 on the substrate 100 and forming a hard mask layer 102 on the first gate ...
Claims
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IPC IPC(8): H01L27/11521H01L27/11531H10B41/30H10B41/42
CPCH10B69/00
Inventor 周儒领张庆勇
Owner SEMICON MFG INT (SHANGHAI) CORP