Programmable clock phase shift circuit

Abstract

The invention discloses a programmable clock phase shift circuit, which belongs to the technical field of electronic circuits. According to the clock phase shift circuit, by controlling and adjusting currents in pseudo inverters on a clock signal link by programming, charging and discharging time of an integrating capacitor is controlled, then by the positive feedback action of a first schmitt trigger SMIT1 and a second schmitt trigger SMIT2, adjustment of a falling edge or a rising edge is accelerated, and finally the adjustment on the phase of an input clock signal by a first pseudo inverter INVW1 and a second pseudo inverter INVW2 is realized; by only simple programming, charging currents of different proportions can be provided for the capacitor, transmission precision is ensured, meanwhile, the overhead of a chip area and circuit design difficulty are greatly reduced, and circuit power consumption is reduced. 8 phase shifts which are from 0 degree to 315 degrees and have a step length of 45 degrees of the clock can be realized, and the requirements of an optimal time sequence adjusting position of the later stage circuit can be met fastest.

Description

technical field [0001] The present invention relates to a programmable clock phase-shift circuit, in particular to a clock phase-shift circuit that can realize phase shift from 0° to 315° with a step size of 45° through fast programming through a three-bit logic signal, belonging to an integrated circuit technology field. Background technique [0002] In the application field of semiconductor integrated circuits, especially in analog-digital mixed-signal chip circuits, the digital output usually jumps at the same time as the falling or rising edge of the output clock CLKOUT, so the falling or rising edge can be used to lock the output data. For example, in a pipelined analog-to-digital converter, in order to obtain sufficient rise and fall time when outputting locked data, it is necessary to phase-shift the CLKOUT signal relative to the data output bit to meet the sampling requirements of the subsequent FPGA circuit. The best position to adjust the timing. In the implement...

AI Technical Summary

Problems solved by technology

[0003] When transmitting multi-phase clocks, in order to transmit output clocks of different phases, different phase-shift capacitor arrays and multiple transmission dedicated lines need to be designed, which greatly increases the chip layout area

At the same time, if the transmission line distance is long, or the transmission path gap between each phase shift is large, and other signals interfere with the output clock transmission, etc., there will be a large time lag between the clock phase shifts of each phase.

At that time, when the output clock frequency was high, it would even lead to distortion of the clock duty cycle of each phase shift, so that the normal locking data of the output clock could not be guaranteed, resulting in missing codes or code errors in signal acquisition.

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