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Silicon carbide substrate structure with trench array and cavity

A silicon carbide substrate and array technology, applied in electrical components, circuits, semiconductor devices, etc., can solve difficult problems such as silicon carbide substrate thinning process, so as to alleviate thermal stress problems, reduce substrate resistance, and debris The effect of reducing the chance of

Inactive Publication Date: 2017-07-18
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it is difficult to complete the silicon carbide substrate thinning process with ordinary process lines

Method used

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  • Silicon carbide substrate structure with trench array and cavity
  • Silicon carbide substrate structure with trench array and cavity
  • Silicon carbide substrate structure with trench array and cavity

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] figure 2 is a schematic cross-sectional view of a silicon carbide junction barrier Schottky diode, wherein the diode adopts the substrate structure provided by the present invention. It includes a silicon carbide substrate 1, which is an N-type silicon carbide material in this embodiment; the top surface of the substrate P1; the bottom surface of the substrate P2; the trench array 2; the first layer of metal 3; the second layer of metal 5; silicon carbide epitaxy Layer 6, which is N-type semiconductor in this embodiment; heavily doped region 7, which is P-type semiconductor in this embodiment; passivation layer 8; Schottky barrier metal 9.

[0048] image 3 is the bottom view of the device after the trench array has been etched. In this embodiment, all the trenches are distributed in a grid pattern, and the trenches in each row are in the same column position. In this embodiment, the groove array occupies nearly 1 / 5 of the total area of ​​the substrate bottom surfac...

Embodiment 2

[0063] figure 2 is a schematic cross-sectional view of a silicon carbide junction barrier diode, wherein the diode adopts the substrate structure provided by the present invention. Including silicon carbide substrate 1, in this embodiment is N-type silicon carbide material; substrate top surface P1; substrate bottom surface P2; trench array 2; ohmic contact layer metal 3; solder layer metal 5; silicon carbide epitaxial layer 6, N-type semiconductor in this embodiment; heavily doped region 7, P-type semiconductor in this embodiment; passivation layer 8; Schottky barrier metal 9.

[0064] Figure 4 is the bottom view of the device after the trench array has been etched. In this embodiment, all the trenches are distributed in a grid pattern, and the column positions of the trenches in two adjacent rows are staggered. In this embodiment, the groove array occupies nearly 1 / 5 of the total area of ​​the substrate bottom surface P2.

[0065] A possible manufacturing process of th...

Embodiment 3

[0073] figure 2 is a schematic cross-sectional view of a silicon carbide junction barrier diode, wherein the diode adopts the substrate structure provided by the present invention. Including silicon carbide substrate 1, in this embodiment is N-type silicon carbide material; substrate top surface P1; substrate bottom surface P2; trench array 2; ohmic contact layer metal 3; solder layer metal 5; silicon carbide epitaxial layer 6, N-type semiconductor in this embodiment; heavily doped region 7, P-type semiconductor in this embodiment; passivation layer 8; Schottky barrier metal 9.

[0074] Figure 5 is the bottom view of the device after the trench array has been etched. In this embodiment, all the grooves are distributed in a honeycomb shape. In this embodiment, the groove array occupies nearly 1 / 5 of the total area of ​​the substrate bottom surface P2.

[0075] A manufacturing process that can be used for the device includes the following steps.

[0076] In the first step...

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Abstract

The invention discloses a silicon carbide substrate structure with a trench array and a cavity. The structure comprises a silicon carbide substrate, the trench array disposed on the bottom surface of the silicon carbide substrate, and a metal lamination layer which is disposed on the bottom surface of the silicon carbide substrate and covers the trench array. The metal lamination layer comprises a first metal layer covering the bottom surface of the substrate and the bottom surface of the trench array, and a second metal layer, wherein the upper surface of the second metal layer is connected with the bottom surface of the first metal layer and the lower surface of the second metal layer forms the cavity on the trench array. The structure reduces the resistance of a substrate layer, and is compatible with the common production line. The structure maintains the complete substrate thickness, reduces the fragment occurrence probability, and alleviates the thermal stress problem in a heat circulation process or an actual application process.

Description

technical field [0001] The present invention relates to semiconductor power devices, and more particularly, the present invention relates to a silicon carbide substrate structure with groove arrays and cavities. Background technique [0002] In recent years, more and more attention has been paid to energy saving and emission reduction in the world, which puts forward higher requirements for loss control and efficiency improvement of large power electronic equipment. As an important part of power electronic equipment, semiconductor power devices have received extensive attention from the industry. Reducing the on-resistance of semiconductor power devices is an important means to improve the efficiency of power electronic equipment. [0003] With the continuous development of semiconductor power devices, device performance has gradually improved. As a new type of wide-bandgap semiconductor material, silicon carbide is expected to further reduce the on-resistance when used in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/16H01L29/872
CPCH01L29/10H01L29/1608H01L29/872
Inventor 王珩宇盛况
Owner ZHEJIANG UNIV
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