Phase discriminator and clock and data recovery circuit

Abstract

The invention discloses a phase discriminator and a clock and data recovery circuit. The phase discriminator comprises a data sampling circuit for performing baud rate sampling on a data flow to obtain a data sampling sequence; an integral composition circuit for performing integral composition on the data flow to obtain a quantized digital signal; a logic circuit for outputting a corresponding level signal according to the data sampling sequence and the quantized digital signal.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a phase detector and a clock and data recovery circuit. Background technique [0002] In various data transmission interface circuits, the receiving end needs to retime the data sent by the sending end through a Clock and Data Recovery (CDR) circuit. In the CDR circuit, it is necessary to use a phase detector to judge the phase relationship between the recovered clock signal and the data symbols, so as to adjust the clock signal through a feedback loop to obtain an optimal sampling point. [0003] The Bang-Bang phase detector is a kind of phase detector commonly used in the CDR circuit at present. The circuit structure of the traditional Bang-Bang phase detector is as follows: figure 1 as shown, figure 1 It is a circuit structure diagram of a traditional Bang-Bang phase detector, which includes a data sampling circuit, an edge sampling circuit and a logic circuit. Its basic ...

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Problems solved by technology

[0011] The embodiment of the present invention provides a phase detector and a clock and data recovery circuit to at least solve the technical problem of high power consumption caused by the CDR circuit of the traditional Bang-Bang phase detector in the existing process of acquiring edge sampling information

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