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Surface planarization method for interlayer dielectric, and semiconductor structure based on interlayer dielectric

A technology of interlayer dielectric layer and conductor structure, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. Thickness, the effect of improving yield

Active Publication Date: 2017-11-28
CHANGXIN MEMORY TECH INC
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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for flattening the surface of an interlayer dielectric layer and a semiconductor structure based thereon, which are used to solve the problem of scratching when the surface of the interlayer dielectric layer is planarized in the prior art. Defects such as damage and high cost

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  • Surface planarization method for interlayer dielectric, and semiconductor structure based on interlayer dielectric
  • Surface planarization method for interlayer dielectric, and semiconductor structure based on interlayer dielectric
  • Surface planarization method for interlayer dielectric, and semiconductor structure based on interlayer dielectric

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Embodiment Construction

[0049] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] see Figure 1 to Figure 5 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and ...

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Abstract

The invention provides a method for flattening the surface of an interlayer dielectric layer, comprising the steps of: providing a semiconductor structure, and predefining the required first thickness of the interlayer dielectric layer, and forming a layer with a second thickness on the upper surface of the unit integration layer of the semiconductor structure The first interlayer dielectric layer, the first thickness is less than the second thickness; the first interlayer dielectric layer is excessively ground, and the first interlayer dielectric layer is thinned to a third thickness to obtain a first interlayer dielectric with a flattened surface layer, the grinding liquid is an acidic grinding liquid, and the third thickness is smaller than the first thickness; Compensation deposition is performed on the surface of the first interlayer dielectric layer to form a second interlayer dielectric layer with a fourth thickness, which is separated from the first layer The superposition of the dielectric layer is an interlayer dielectric layer required by the semiconductor structure, and the fourth thickness is less than or equal to the third thickness. Through the above solution, the present invention can reduce scratches generated in the interlayer dielectric layer, improve product yield, reduce production cost, and realize precise control of the thickness of the interlayer dielectric layer.

Description

technical field [0001] The invention belongs to the technical field of semiconductor technology, in particular to a method for flattening the surface of an interlayer dielectric layer and a semiconductor structure based thereon. Background technique [0002] With the continuous development of semiconductor technology and the continuous increase of interconnection layers in large-scale integrated circuits, the planarization technology of conductive layers and insulating dielectric layers has become particularly critical. In the 1980s, the chemical mechanical polishing (CMP) technology pioneered by IBM is considered to be the most effective method for global planarization. [0003] The chemical mechanical polishing (CMP) process is to use mechanical force to act on the surface of the wafer in the atmospheric environment of the clean room to generate fracture corrosion power on the surface film layer, so that the surface of the wafer tends to be flattened, so that Perform subs...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B37/04B24B37/10B24B37/005B24B49/16B24B41/00H01L21/768H01L23/528
CPCB24B37/042B24B37/005B24B37/107B24B41/007B24B49/16H01L21/76819H01L23/5283
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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