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High-throughput FFT/IFFT-based FPGA signal processing method

A high throughput and signal processing technology, applied in the field of FPGA technology, can solve the problems of consuming hardware resources, less DFT transformation throughput, etc., and achieve the effects of reducing hardware consumption, easy engineering implementation, and reducing parallelism

Active Publication Date: 2017-12-08
电信科学技术第五研究所有限公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] Since cooley-tukey proposed the DFT fast algorithm, there has been more in-depth research on the DFT algorithm, mainly including the prime factorization method, the winogard algorithm (WFTA), the circular convolution algorithm, etc., but these algorithms mainly focus on the DFT transformation itself, and there are few studies on it. Research on the throughput of DFT transformation. When higher throughput is required, FPGA usually implements it in parallel processing.
[0004] When the FPGA implementation of the prior art is implemented, simply adopting a parallel method to improve the FFT throughput rate will consume a large amount of hardware resources

Method used

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Embodiment 1

[0021] This embodiment only illustrates the steps of writing / reading / outputting the RAM.

[0022] The RAM storage area reading and writing mode of the present invention refers to Figure 4 , the RAM is regarded as a circular arrangement of multiple storage areas, and each storage area is sequentially numbered 1, 2, 3... in a clockwise direction. Figure 4 is a simplified schematic diagram containing 32 memory areas. First read the data from the 30MHz low-frequency signal, and write the read data content to the storage area sequentially and cyclically in the order of the storage area, that is, after the storage area with the serial number 32 is written, the storage area with the serial number 1 As a continuation, a loop is formed. The read clock is high frequency, such as 150MHz higher than 30MHz, and the data is read from the RAM in the form of a sliding window. Figure 4 The length of the middle sliding window is 8 storage areas, and the sliding step is 1 storage area.

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Embodiment 2

[0029] Assuming that the input signal with a rate of 30MHz is x(n)n=0,1,2,..., a vector with a length of 64 at every other sampling point needs to perform a 64-point FFT operation, that is, the vector [x(0)x (1)...x(63)] needs to perform a 64-point FFT, and the vector [x(1)x(2)...x(64)] needs to perform a 64-point FFT, and the vector [x(2)x(3)... x(65)] requires a 64-point FFT.

[0030] To the FPGA realization of the above-mentioned problem, the present invention adopts the mode that data rate multiplication and parallel processing combine to calculate, and its realization block diagram is as follows Figure 1 to Figure 3 as shown, figure 1 Indicates that the 30MHz signal is converted into a 150MHz signal, and the signal rate is increased by 5 times, so that subsequent modules can operate at a higher frequency; figure 2 Indicates the rate conversion control diagram, which controls the input and output signal addresses, image 3 It means that the above calculation is realiz...

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Abstract

The invention discloses a high-throughput FFT / IFFT-based FPGA signal processing method and relates to an FPGA technology. The method comprises the following steps of 1) reading data of a low-frequency signal; 2) writing contents of the data of the low-frequency signal into a first storage region and other storage regions of an RAM in sequence; 3) under the control of a high-frequency read clock, reading the data contents written into the storage regions in sequence through a sliding window, and outputting the data contents in the sliding window in sequence to form data flow; and 4) from a starting moment of the data flow, enabling an Nth FPGA to enter a data processing stage after (N-1) waiting cycles to read the data flow, performing FFT calculation, and outputting a calculation result. Through the RAM, low-rate data is converted into high-rate data, so that subsequent modules can work at a relatively high frequency, the purpose of reducing degree of parallelism is achieved, and finally the hardware consumption is reduced. The method is simple in algorithm and easy for engineering realization.

Description

technical field [0001] The present invention relates to FPGA technology. Background technique [0002] Discrete fourier transform (DFT for short) and inverse discrete fourier transform (IDFT for short) are important transformation tools in the field of digital signal processing, both in signal spectrum analysis and OFDM system modulation and demodulation It is realized by DFT / IDFT. However, direct calculation of DFT / IDFT requires a lot of calculations. Its fast algorithm (fast fourier transform referred to as FFT) uses the properties of Fourier transform coefficients to greatly reduce the amount of multiplication operations, making Fourier transform widely used in engineering. [0003] Since cooley-tukey proposed the DFT fast algorithm, there has been more in-depth research on the DFT algorithm, mainly including the prime factorization method, the winogard algorithm (WFTA), the circular convolution algorithm, etc., but these algorithms mainly focus on the DFT transformation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14G06F12/06
CPCG06F12/06G06F17/14
Inventor 舒勇翟大海王昌庆
Owner 电信科学技术第五研究所有限公司
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