Md5 brute force cracking system and method based on fpga

Abstract

The invention discloses a MD5 brute force cracking system and method based on FPGA. The system comprises an input interface unit, a N-core MD5 cracking operation unit and an output interface unit connected in order, wherein the N-core MD5 brute force cracking operation unit is composed of N single-core MD5 brute force cracking operation units in parallel connection; by adopting the multi-core parallel processing mechanism, various single cores simultaneously generates the keys in parallel, after the MD5 operation, the hash value matching is performed to respectively obtain the matching result; the single-core MD5 brute force cracking operation unit comprises a key strategy generation module, and a MD5 algorithm operation module, and a hash value matching module. The system disclosed by the invention maximally reduces the limitation on the FPGA clock operation frequency by the MD5 algorithm, the clock frequency of realizing the MD5 brute force cracking algorithm operation by the FPGA is improved, and the MD5 brute force cracking rate is improved exponentially by using the design thought of multi-core parallel processing mechanism, and a problem that the MD5 brute force cracking efficiency is low is solved.

Description

technical field [0001] The invention relates to the technical field of information security, in particular to an FPGA-based MD5 brute force cracking system and method. Background technique [0002] A brief description of the MD5 algorithm: MD5 uses 512-bit packets to process input information, and each packet is divided into 16 32-bit sub-packets. After a series of processing, the output of the algorithm consists of four 32-bit packets. After concatenating these four 32-bit packets, a 128-bit hash value is generated, which is unique. [0003] The MD5 main loop has 4 rounds, and each round is very similar. 16 operations are performed in each round, that is, 16 steps of operations; the first round is 16 operations of FF(a,b,c,d,Mj,s,ti), and the second round is 16 operations of GG(a,b, c, d, Mj, s, ti) operation, the third round is 16 HH (a, b, c, d, Mj, s, ti) operation, the fourth round is 16 times II (a, b, c, d, Mj, s, ti) operations, and finally output a 128-bit hash v...

AI Technical Summary

Problems solved by technology

[0005] The patent search of the existing technology found that the patent No. 201110099441 "Ultra-high throughput md5 brute force cracking device based on FPGA" provides a design method for brute force cracking MD5 algorithm based on FPGA hardware. The defect of this patent lies in: MD5 brute force cracking One core computing unit, one-level pipeline processing for each calculation, that is, 64-level pipeline processing 64 operation calculations (4 rounds of MD5 main loop, 64 operation calculations), one operation single-stage pipeline processing limits MD5 brute force cracking operations in FPGA The operating rate of the FPGA, which limits the clock frequency of the FPGA, and the patent is a single-core MD5 brute force crack

Another existing public patent "Hardware-implemented MD5function" proposes an FPGA-based design method, but the 64-stage pipeline processing implementation of the MD5 core algorithm limits the clock frequency of the FPGA. There is only a single-core MD5 brute-force cracking operation unit, and there is no parallel multi-core MD5 operation. unit processing

Patent No. 3 / 440,264 "Efficient Implementation of HashAlgorithm on a Processor" proposes a solution based on the ARM processor to implement the MD5 algorithm. The defect of this patent is that the speed and efficiency of the ARM processor are not as good as FPGA, and it is also a single-core MD5 brute-force cracking operation unit.

Another existing public patent "File Password Cracking Method" proposes an exhaustive cracking solution based on PC. PC is a serial processing mechanism and can only handle single-core MD5 brute force cracking computing units, while FPGA is parallel processing, and at the same time Multi-core MD5 brute-force cracking operation units can be processed in parallel, so the design flaw of this patent is that MD5 brute-force cracking takes a long time and is inefficient

[0006] To sum up, the prior art does not involve the multi-core processing mechanism of the MD5 brute force operation unit based on FPGA hardware technology, nor does it involve the design idea of ​​using single-step operation to operate a multi-stage pipeline; how to improve the speed and efficiency of MD5 brute force operation , how to multi-core MD5 brute force cracking operation unit parallel processing mechanism is the key to improving the data processing rate and data throughput, and it is also the bottleneck to improve the MD5 brute force cracking rate, and it is also a problem to be solved in the existing technology

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