Wafer 3D Integrated Lead Process and Its Structure for 3D Memory
A technology of integrated wires and three-dimensional storage, which is applied in the manufacture of semiconductor devices, electrical solid state devices, and semiconductor/solid state devices. It can solve problems such as difficulties in leading out the first metal layer, reduce production costs, and improve product yields.
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Embodiment 1
[0039] refer to Figure 3-7 As shown, Embodiment 1 of the present invention provides a wafer three-dimensional integrated wiring process, including the following steps:
[0040] A first wafer 11 is provided, the first wafer 11 has a front side and a back side arranged oppositely, and a contact hole area 12 is provided on at least a part of the front side of the first wafer 11;
[0041] A dielectric layer 13 is formed in the contact hole region 12. Preferably, the dielectric layer has a thickness ranging from 0.3 microns to 5 microns. More preferably, the dielectric layer has a thickness of about 1 micron. The dielectric layer 13 is an oxide A dielectric layer 13 or a nitride dielectric layer 13, the process of forming the dielectric layer 13 in the contact hole region 12 includes one of lithography, etching, deposition, filling and grinding or any combination thereof, the dielectric layer has an oppositely arranged top A surface and a bottom surface, wherein the top surface i...
Embodiment 2
[0050] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.
[0051] refer to image 3 As shown, the dielectric layer 13 has a bottom surface and a top surface oppositely disposed, and the bottom surface is a side farther away from the first metal layer 18 than the top surface. Preferably, the dielectric layer has a thickness ranging from 0.3 microns to 5 microns, more preferably, the dielectric layer has a thickness of about 1 micron. In the step of forming the dielectric layer 13, at first, a trench is formed in the contact hole area 12 on the front surface of the first wafer 11 through lithography and etching processes, and the depth of the trench cannot be too shallow or too deep. Deep, the dielectric layer formed by too shallow depth is too thin to effectively complete the subsequent process of forming the metal connection structure, and the dielectric layer formed by too deep depth is too thick fo...
Embodiment 3
[0061] In this embodiment, the parts different from the above embodiments will be described, and the same parts will not be repeated.
[0062] The dielectric layer 13 has a bottom surface and a top surface opposite to each other, and the bottom surface is a side farther away from the first metal layer 18 than the top surface. Preferably, the dielectric layer has a thickness ranging from 0.3 microns to 5 microns, more preferably, the dielectric layer has a thickness of about 1 micron. In the step of forming the dielectric layer 13, at first, a trench is formed in the contact hole region 12 on the front surface of the first wafer 11 through lithography and etching processes, and then a trench is formed in the trench by deposition and filling processes. The dielectric layer 13 is formed, and the dielectric layer 13 may be polished to be planarized by a grinding process subsequently. After the above process steps, the bottom surface of the formed dielectric layer 13 is located in...
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