3D NAND flash memory channel hole preparing method and 3D NAND flash memory

Abstract

The invention provides a 3D NAND flash memory channel hole preparing method and 3D NAND flash memory. The method comprises the steps of conducting deposition in a channel hole of a substrate stackingstructure, and respectively forming a blocking layer, an accumulating layer, and a tunneling layer; conducting deposition of a first polysilicon layer; conducting low-temperature free radical oxidation on the polysilicon layer of the first deposition, and forming a masking oxide layer; conducting etching on the masking oxide layer, the first polysilicon layer, the tunneling layer, the accumulatinglayer and the blocking layer at the bottom part of the channel hole until a silicon epilayer is exposed and over etching is conducted on the silicon epilayer at a certain depth; Removing the maskingoxide layer and conducting pre-cleaning before the deposition of a second polysilicon layer; conducting deposition on the second polysilicon layer. The invention is advantageous in that as the low-temperature free radical oxidation technology is adopted to form the masking oxide layer and diluted hydrofluoric acid is adopted to conduct the pre-cleaning of the second polysilicon layer before deposition, the step of etchback of the polysilicon can be saved, and the channel hole polysilicon layer with good uniformity and high quality can be formed, and cost is low and reliability is high.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing 3D NAND flash memory channel hole polysilicon. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, research on memory devices with a three-dimensional (3D) structure has gradually heated up this year, and integration density is increased by three-dimensionally arranging memory cells on a substrate. [0003] In the production of 3D NAND flash memory, it involves the preparation method of each functional layer of the channel ho...

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Problems solved by technology

[0009] 1) However, in the above method, there are following defects: in the polysilicon wet etching back process in the S2 step, it is difficult to control the uniformity of the polysilicon thickness, such as figure 2 As shown in the photo, the thickness of the polysilicon around the channel hole is 6.66 (nm), 6.84 (nm), 7.02 (nm) and 7.2 (nm) in the four directions of the circumference, the difference is about 8%, and the polysilicon Susceptible to damage, thereby affecting product formation

The barrier oxide layer prepared by the atomic layer deposition method (ALD) used in the S3 step is not dense enough, due to the problems of the process itself, particles and pores are generated in the deposited layer, and the cost is high, and the deposition efficiency is low; it is easy to integrate in the subsequent process Bottom disconnection issues forming polysilicon, such as Figure 3a and 3b As shown, it can be seen that the bottom of the polysilicon layer 1-6 deposited in the second layer is not connected. It can also be seen from the figure that the thickness of the polysilicon deposited in the second layer is inconsistent at different positions. The thickness deposited in the silicon epitaxial layer is the largest, and in the ONO The thickness of the structural part deposited is the smallest (T Si > T a-Si > T ONO )

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