Preparation method of SOI (Silicon-On-Insulator) substrate material and SOI material
A technology of substrate materials and silicon substrates, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of low substrate surface resistivity, affecting device performance, and easy introduction of impurities, etc. Effects of RF substrate loss, increased linearity, and simple process
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Embodiment 1
[0044] This embodiment provides a kind of preparation method of SOI silicon substrate material and SOI material, and this substrate refers to the SOI substrate sheet with intrinsic polycrystalline or intrinsic amorphous silicon layer on the back, and its preparation comprises the following steps:
[0045] 1. Provide high-resistance silicon wafers (silicon wafer resistivity greater than 500ohm.cm), and use DHF, SC1 and SC2 to clean the surface in order to remove the natural oxide layer and pollutants on the silicon wafer surface ( figure 1 (a)).
[0046] 2. Reference figure 1 (b), prepare a silicon oxide layer on the surface of the high-resistance silicon wafer, the thickness of the grown oxide layer
[0047] 3. In figure 1 On the basis of (b), prepare a doped polysilicon layer ( figure 1 (c)), the thickness is 2 μm, the doping type is P type, and the resistivity is 1ohm.cm.
[0048] 4. In figure 1 On the basis of (c), a 2 μm intrinsic polysilicon layer is grown on the b...
Embodiment 2
[0052] This embodiment provides a method for preparing an SOI silicon substrate, which refers to an SOI substrate with an intrinsic polycrystalline or intrinsic amorphous silicon layer on the back, and its preparation includes the following steps:
[0053] 1. Provide high-resistance silicon wafers (silicon wafer resistivity greater than 500ohm.cm), and use DHF, SC1 and SC2 to clean the surface in order to remove the natural oxide layer and pollutants on the silicon wafer surface ( figure 1 (a)).
[0054] 2. Reference figure 1 (b), prepare a silicon oxide layer on the surface of the high-resistance silicon wafer, the thickness of the grown oxide layer
[0055] 3. In figure 1 On the basis of (b), prepare a doped polysilicon layer ( figure 1 (c)), the thickness is 2 μm, the doping type is P type, and the resistivity is 1ohm.cm.
[0056] 4. In figure 1 On the basis of (c), a 2 μm intrinsic amorphous silicon layer is grown on the back. ( figure 1 (d))
[0057] 5. Use fig...
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