Unlock instant, AI-driven research and patent intelligence for your innovation.

A method for optimizing shallow trench morphology in soi and bulk regions of fdsoi devices

An optimization method and device technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of improving process and device performance, eliminating film layer differences, and reducing depth loads

Active Publication Date: 2020-06-16
SHANGHAI HUALI MICROELECTRONICS CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] During the FDSOI multi-layer mask shallow trench isolation etching process, the FDSOI shallow trench isolation process includes the SOI device substrate (HM / SOI / BOX / sub) region and the passive device body (bulk) substrate (HM / silicon) region. Etching, in the original process, the etching program with a small OX / silicon selection ratio is selected to open these two parts at the same time, resulting in a large depth loading in the two regions and an undercut in the OX / sub transition region of the SOI region (undercut) effect

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method for optimizing shallow trench morphology in soi and bulk regions of fdsoi devices
  • A method for optimizing shallow trench morphology in soi and bulk regions of fdsoi devices
  • A method for optimizing shallow trench morphology in soi and bulk regions of fdsoi devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] The specific embodiments of the present invention are given below in conjunction with the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0021] Please refer to figure 1 , figure 1 Shown is a flow chart of the method for optimizing the shallow groove morphology of the SOI and bulk regions of the FDSOI device according to a preferred embodiment of the present invention. The present invention proposes a method for optimizing the shallow groove morphology of the SOI and bulk regions of an FDSOI device, comprising the following steps:

[0022] Step 1 S100: providing an FDSOI device substrate;

...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a shallow slot morphology optimization method of an SOI area and a bulk area of an FDSOI (Fully Depleted Silicon on Insulator) device. The method comprises the followingsteps of: providing a FDSOI device substrate; performing SOI layer etching of the structure mentioned above; performing surface oxidation treatment of the structure mentioned above, and forming an oxidation position at a bulk area; performing etching of an SOI area and the bulk area at the same time to the oxidation position; and performing etching processing of the structure mentioned above, andforming an FDSOI device shallow slot isolation structure. The shallow slot morphology optimization method of the SOI area and the bulk area of the FDSOI device provided by the invention employs a method of multi-time in-situ plasma surface oxidation treatment of the bulk area and then layer-by-layer etching to eliminate film difference of the SOI area and the bulk area, and therefore, indifference etching of the two areas is ensured, it is ensured that morphologies of the two areas after etching are smooth and complete and have no boundary and deformation, depth loads of the two areas are reduced, and finally, process and device performances can be improve and stably controlled.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for optimizing the morphology of shallow grooves in SOI and bulk regions of FDSOI devices. Background technique [0002] With the advancement of technology, integrated circuits have developed to the ultra-large-scale nanoscale stage, and the process of bulk silicon substrates and bulk silicon devices is approaching the physical limit. There are severe challenges in further reducing the feature size of integrated circuits. At present, the industry believes that SOI substrates and SOI devices are one of the best solutions to replace bulk silicon substrates and bulk silicon devices. [0003] FDSOI (fully depleted silicon-on-insulator) refers to the basic technology of replacing traditional silicon-on-insulator (i.e., bulk silicon) with silicon-on-insulator. The FDSOI process can effectively reduce parasitic capacitance and improve operating ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/76221
Inventor 朱轶铮陆连
Owner SHANGHAI HUALI MICROELECTRONICS CORP