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Semiconductor device, manufacturing method thereof and electronic device

A manufacturing method and semiconductor technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as unfavorable short-channel effect and poor lateral phosphorus diffusion ability, and achieve good short-channel effect and improve Performance and yield, the effect of large contact area

Active Publication Date: 2018-04-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, larger SiP epitaxy is not conducive to the control of short channel effects, because the lateral diffusion ability of phosphorus is too poor

Method used

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  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0074] In view of the problems existing in the prior art, the present invention provides a method for manufacturing a semiconductor device, such as Figure 20 As shown, it mainly includes the following steps:

[0075] Step S201, providing a semiconductor substrate, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;

[0076] Step S202, forming a first dummy gate structure and a second dummy gate structure across a part of the first fin structure and a part of the second fin structure in the PMOS region and the NMOS region, respectively;

[0077] Step S203, growing a first stressed epitaxial layer in the source / drain regions of the first fin structure on both sides of the first dummy gate structure;

[0078] Step S204, forming first spacers on both side walls of the second fin structure on both sides of the secon...

Embodiment 2

[0190] The present invention also provides a semiconductor device prepared by using the method in the first embodiment above.

[0191] Specifically, as Figure 17 and Figure 18 As shown, the semiconductor device of the present invention includes a semiconductor substrate 100, the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a first fin structure is respectively formed on the semiconductor substrate 100 in the PMOS region and the NMOS region 1011 and a second fin structure 1012 .

[0192] Specifically, the semiconductor substrate 100 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including these semiconductor components multi-layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI) wait. In this embodiment, the semi...

Embodiment 3

[0222] The present invention also provides an electronic device, including the semiconductor device described in the second embodiment, and the semiconductor device is prepared according to the method described in the first embodiment.

[0223] The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

[0224] in, Figure 20 An example of a mobile phone handset is shown. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection por...

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Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the step of forming astress epitaxial layer in a source / drain region in an NMOS region, wherein the stress epitaxial layer comprises a second stress epitaxial layer and a third stress epitaxial layer, the second stress epitaxial layer is arranged at the bottom and has a first width, the third stress epitaxial layer is arranged on the second stress epitaxial layer and comprises a third stress epitaxial layer having asecond width and a third stress epitaxial layer having a third width from bottom to top, the third stress epitaxial layer having the third width is arranged on a top surface of a second gap wall, thefirst width is smaller than the second width, the second width is smaller than the third width, thus, the top of the stress epitaxial layer is expanded, the contact area is larger, and the stress epitaxial layer has relatively low external resistance; and moreover, the volume of the stress epitaxial layer at the bottom is not expanded, the short channel effect also can be controlled very well, andthe performance and the yield of the device are further improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] In the field of semiconductor technology, with the rapid development of nano-processing technology, the feature size of transistors has entered the nanoscale. The method of improving the performance of the current mainstream silicon CMOS devices by scaling down is subject to more and more physical and technological limitations. In order to improve the performance of NMOS and PMOS transistors in CMOS devices, stress engineering has attracted more and more attention from the industry. [0003] Stress affects the mobility of carriers in semiconductors. In general, the mobility of electrons in silicon increases with increasing tensile stress along the direction of electron migration and decreases with increasing compressive stress. In contrast, the mobilit...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823814H01L21/823821H01L27/0924
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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