Semiconductor device, manufacturing method thereof and electronic device
A manufacturing method and semiconductor technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as unfavorable short-channel effect and poor lateral phosphorus diffusion ability, and achieve good short-channel effect and improve Performance and yield, the effect of large contact area
Active Publication Date: 2018-04-27
SEMICON MFG INT (SHANGHAI) CORP +1
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AI-Extracted Technical Summary
Problems solved by technology
In addition, larger SiP epitaxy is not conducive to the control of short cha...
Method used
[0086] According to the manufacturing method of the present invention, when the stress epitaxial layer is grown in the source/drain region of the NMOS region, the spacer is used as a guide, so the merged epitaxial layer (merged epitaxy) will not be formed. In addition, since the top of the stressed epitaxial layer is enlarged , so that the contact area is larger, so the stressed epitaxial layer has a lower external resistance. Moreover, since the volume of the bottom stressed epitaxial layer is basically not increased, the short channel effect is also well controlled. Therefore, according to The manufacturing method of the invention reasonably balances the volume and profile of the source/drain stress epitaxial layer, and improves the performance and yield of the device.
[0109] Among them, the LDD ion implantation to form a lightly doped drain (LDD) structure in the source/drain region can reduce the electric field and significantly improve the hot electron effect.
[0188] According to the manufacturing method of the present invention, the spacer is used as a guide when growing the stress epitaxy layer in the source/drain region of the NMOS region, so the merged epitaxy layer (merged epitaxy) will not be formed. In addition, due to the expansion of the to...
Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the step of forming astress epitaxial layer in a source/drain region in an NMOS region, wherein the stress epitaxial layer comprises a second stress epitaxial layer and a third stress epitaxial layer, the second stress epitaxial layer is arranged at the bottom and has a first width, the third stress epitaxial layer is arranged on the second stress epitaxial layer and comprises a third stress epitaxial layer having asecond width and a third stress epitaxial layer having a third width from bottom to top, the third stress epitaxial layer having the third width is arranged on a top surface of a second gap wall, thefirst width is smaller than the second width, the second width is smaller than the third width, thus, the top of the stress epitaxial layer is expanded, the contact area is larger, and the stress epitaxial layer has relatively low external resistance; and moreover, the volume of the stress epitaxial layer at the bottom is not expanded, the short channel effect also can be controlled very well, andthe performance and the yield of the device are further improved.
Application Domain
TransistorSolid-state devices +1
Technology Topic
External resistanceShort-channel effect +4
Image
Examples
- Experimental program(3)
Example Embodiment
[0073] Example one
[0074] In view of the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, such as Picture 20 As shown, it mainly includes the following steps:
[0075] Step S201, providing a semiconductor substrate, the semiconductor substrate including a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;
[0076] Step S202, forming a first dummy gate structure and a second dummy gate structure across part of the first fin structure and part of the second fin structure in the PMOS region and the NMOS region, respectively;
[0077] Step S203, growing a first stressed epitaxial layer in the source/drain regions of the first fin structure on both sides of the first dummy gate structure;
[0078] Step S204, forming first spacers on both sidewalls of the second fin structure on both sides of the second dummy gate structure;
[0079] Step S205, performing a first etch back on the exposed source/drain regions of the second fin structure to remove part of the second fin structure to form a first groove;
[0080] Step S206, reducing the thickness of the first gap wall to expand the width of the first groove to a first width;
[0081] Step S207, growing a second stressed epitaxial layer on the second fin structure exposed in the first groove to fill the first groove, wherein the width of the second stressed epitaxial layer is the First width
[0082] Step S208, forming a second spacer on the sidewalls of the second fin structure and the second stress epitaxial layer;
[0083] Step S209, removing part of the second stressed epitaxial layer by a second etch-back to form a second groove;
[0084] Step S210, reducing the thickness of the second gap wall to expand the width of the second groove to a second width;
[0085] Step S211, growing a third stressed epitaxial layer on the surface of the second stressed epitaxial layer to fill the second groove and overflow to the top surface of the remaining second spacer, wherein The width of the third stressed epitaxial layer in the second groove is the second width, and the third stressed epitaxial layer located above the top surface of the second spacer has a third width, wherein the first A width is smaller than the second width, and the second width is smaller than the third width.
[0086] According to the manufacturing method of the present invention, spacers are used as a guide when the stress epitaxy layer is grown in the source/drain regions of the NMOS region. Therefore, a merged epitaxy is not formed. In addition, the top of the stress epitaxy is enlarged to make contact The area is larger, so the stressed epitaxial layer has lower external resistance. Moreover, since the volume of the bottom stressed epitaxial layer is not basically increased, the short channel effect is also well controlled. Therefore, according to the present invention The manufacturing method reasonably balances the volume and profile of the source/drain stress epitaxial layer, and improves the performance and yield of the device.
[0087] Below, reference Figure 1 to Figure 18 The manufacturing method of the semiconductor device of the present invention is described in detail, in which, Figure 1 to Figure 18 It shows a cross-sectional view of a structure formed in relevant steps of a method for manufacturing a semiconductor device in an embodiment of the present invention.
[0088] Specifically, first, as figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a PMOS region and an NMOS region. A first fin structure 1011 and a second fin are formed on the semiconductor substrate 100 in the PMOS region and the NMOS region, respectively. 片结构1012。 Sheet structure 1012.
[0089] Specifically, the semiconductor substrate 100 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, as well as these semiconductor components. Multi-layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI) Wait. In this embodiment, the semiconductor substrate 100 is preferably a silicon substrate.
[0090] A first fin structure 1011 is formed on the semiconductor substrate 100 in the PMOS region, and a second fin structure 1012 is formed on the semiconductor substrate 100 in each NMOS region.
[0091] In an example, the method of forming the first fin structure 1011 and the second fin structure 1012 includes the following steps:
[0092] A patterned mask layer is formed on the surface of the semiconductor substrate 100, and the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including fins Using the patterned mask layer as a mask, the semiconductor substrate 100 is etched to form the first fin structure 1011 and the second fin structure 1012. The mask layer may generally include any one of several mask materials, including but not limited to: hard mask materials and photoresist mask materials. The above-mentioned etching can be performed by a method such as dry etching or wet etching, wherein the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may be used, or more than one etching method may be used.
[0093] It should be noted that the method of forming the first fin structure 1011 and the second fin structure 1012 is only exemplary, and is not limited to the above method.
[0094] The widths of the fin structures are all the same, or the fins are divided into multiple fin structure groups with different widths, and the length of the fin structures may also be different.
[0095] An isolation structure 102 is also formed on the semiconductor substrate 100. The isolation structure 102 may be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. In this embodiment, the isolation structure 102 is preferably shallow. Trench isolation structure. The top surface of the isolation structure 102 is lower than the top surfaces of the first fin structure 1011 and the second fin structure 1012. Various well structures are also formed in the semiconductor substrate 100. For example, an N-type well is formed in the PMOS region, and a P-type well is formed in the NMOS region. For simplicity, the illustration is omitted.
[0096] Then, like image 3 As shown, a first dummy gate structure and a second dummy gate structure spanning part of the first fin structure 1011 and part of the second fin structure 1012 are formed in the PMOS region and the NMOS region, respectively.
[0097] Exemplarily, both the first dummy gate structure and the second dummy gate structure include a dummy gate dielectric layer 1031 and a dummy gate material layer 1032.
[0098] It should be pointed out that the term "across" used in the present invention, for example, a gate structure (for example, a dummy gate structure) that straddles a fin structure (for example, a first fin structure, a second fin structure, etc.) , Means that a gate structure is formed on both the upper surface and the side surface of the part of the fin structure, and the gate structure is also formed on a part of the surface of the semiconductor substrate.
[0099] In an example, such as figure 2 As shown, the dummy gate dielectric layer 1031 can be sequentially deposited on the semiconductor substrate 100 first.
[0100] Wherein, the dummy gate dielectric layer 1031 may be silicon oxide (SiO 2 ) Or silicon oxynitride (SiON). An oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ water vapor oxidation (ISSG), etc., can be used to form the dummy gate dielectric layer 1031 made of silicon oxide. The nitridation process on silicon oxide can form silicon oxynitride, wherein the nitridation process can be high temperature furnace tube nitridation, rapid thermal annealing nitridation or plasma nitridation. Of course, other nitridation processes can also be used. I won't repeat it here. The dummy gate dielectric layer 1031 can also be formed by other chemical vapor deposition methods and physical vapor deposition methods.
[0101] In one example, a dummy gate dielectric layer 1031 is formed on all surfaces of the exposed first fin structure 1011 and the second fin structure 1012.
[0102] Then, like image 3 As shown, a dummy gate material layer 1032 is formed on the dummy gate dielectric layer 1031, and chemical mechanical polishing is performed to obtain a flat surface.
[0103] The dummy gate material layer 1032 can be selected from commonly used semiconductor materials in the field, such as polysilicon, etc., and is not limited to a certain one, and will not be listed here.
[0104] The deposition method of the dummy gate material layer includes chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), generally similar methods such as sputtering and physical vapor deposition (PVD) can also be used.
[0105] Then the dummy gate dielectric layer 1031 and the dummy gate material layer 1032 are patterned to form a first dummy gate structure and a second dummy gate structure. Specifically, a hard mask layer 11 is formed on the dummy gate material layer, and then a photoresist layer is formed on the hard mask layer 11, and then exposed and developed to form an opening, and then the photoresist layer is used as The hard mask layer 11 and the dummy gate material layer 1032 are etched by the mask.
[0106] Afterwards, it is also possible to selectively form offset spacers (not shown) on the sidewalls of the first dummy gate structure and the second dummy gate structure.
[0107] Specifically, the offset sidewall spacer may be one of silicon oxide, silicon nitride, and silicon oxynitride or a combination thereof. As an implementation of this embodiment, the offset sidewall spacers are composed of silicon oxide and silicon nitride. The specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer on a semiconductor substrate. The silicon dioxide layer is then etched to form offset spacers. It is also possible to form sidewall material layers on both the top surface and the sidewalls of the dummy gate structure. In the subsequent steps, the sidewall material layer on the top surface is removed by a planarization method, such as chemical mechanical polishing, to form only An offset side wall located on the side wall.
[0108] Subsequently, LDD ion implantation is performed on the PMOS region and the NMOS region respectively.
[0109] Among them, LDD ion implantation to form a lightly doped drain (LDD) structure in the source/drain region can reduce the electric field and can significantly improve the hot electron effect.
[0110] Exemplarily, LDD ion implantation is performed on the first fin structure 1011 on both sides of the first dummy gate structure in the PMOS region to form a P-type lightly doped drain (LDD), and the implanted ions can be any P-type Doping ions include but are not limited to boron (B) ions and indium (In) ions.
[0111] Then perform LDD ion implantation on the second fin structure 1012 on both sides of the second dummy gate structure in the NMOS region to form an N-type lightly doped drain (LDD), and the implanted ions can be any suitable N-type doping Ions include but are not limited to phosphorus (P) ions and arsenic (As) ions.
[0112] Then, like Figure 4 As shown, a first spacer material layer 104 is deposited to cover the PMOS region and the NMOS region.
[0113] Specifically, the first spacer material layer 104 is formed on the surface of the exposed isolation structure 102, on the top surface and sidewalls of the first dummy gate structure and the second dummy gate structure, and the first dummy gate The sidewalls and top surfaces of the first fin structure 1011 and the second fin structure 1012 on both sides of the structure and the second dummy gate structure.
[0114] The first spacer material layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the first spacer material layer 104 is silicon nitride.
[0115] The first spacer material layer 104 may be formed using methods including but not limited to: chemical vapor deposition method and physical vapor deposition method.
[0116] Then, like Figure 5 As shown, a patterned first photoresist layer 1051 is formed to cover the NMOS region and expose the PMOS region.
[0117] Specifically, the patterned first photoresist layer 1051 is formed using a photolithography process (including processes such as coating photoresist, exposure and development), and the patterned first photoresist layer 1051 exposes the PMOS area The first spacer material layer 104.
[0118] Subsequently, using the patterned first photoresist layer 1051 as a mask, etching is removed on the top surface of the first fin structure 1011 and on the surface of the semiconductor substrate 100 (that is, the surface of the isolation structure 102). Part of the first spacer material layer 104 in the above), leaving the first dummy gate structure on the sidewalls and the first fin structure 1021 on both sides of the first dummy gate structure A spacer material layer 104.
[0119] The etching method may use any suitable dry etching or wet etching method well known to those skilled in the art.
[0120] Afterwards, continue as Figure 5 As shown, part of the first fin structure 1011 in the source/drain region on both sides of the first dummy gate structure and part of the first spacer on the first fin structure 1011 are removed by etching back Material layer 104.
[0121] The etching back can use any suitable dry etching or wet etching methods well known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. It is best to perform dry etching through one or more RIE steps.
[0122] After that, the patterned first photoresist layer 1051 is removed. The first photoresist layer 1051 can be removed by an ashing method.
[0123] Then, like Image 6 As shown, a first stressed epitaxial layer 106 is grown in the source/drain regions of the first fin structure 1011 on both sides of the first dummy gate structure.
[0124] The first stressed epitaxial layer 106 can be grown on the exposed surface of the first fin structure 1011 using a selective epitaxial growth method. The selective epitaxial growth can be low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), one of ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).
[0125] The material of the first stressed epitaxial layer 106 may include SiGe or other suitable materials that can provide compressive stress. Specifically, a chemical vapor deposition method or a gas source molecular beam epitaxy method can be used to grow SiGe, using silane or disilane as the silicon source, and adding a certain amount of germane at the same time. For example, choose GeH 4 And SiH 2 Cl 2 As the reaction gas and select H 2 As the carrier gas, the flow ratio of the reaction gas and the carrier gas is 0.01-0.1, the deposition temperature is 300-1000°C, preferably 650-750°C, and the gas pressure is 1-50 Torr, preferably 20-40 Torr.
[0126] A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying compressive stress to the PMOS.
[0127] Among them, preferably, the cross-sectional shape of the first stress epitaxial layer 106 is preferably a "Σ" shape.
[0128] Then, like Figure 7 As shown, an oxidation treatment is performed to form a first oxide layer 107 on the exposed surface of the first stressed epitaxial layer 106.
[0129] The first oxide layer 107 made of silicon oxide can be formed by oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ water vapor oxidation (ISSG), etc.
[0130] Then, continue as Figure 7 As shown, a second spacer material layer 1081 is deposited to cover the PMOS region and the NMOS region.
[0131] The second spacer material layer 1081 can use the same material as the aforementioned first spacer material layer 104, and the second spacer material layer 1081 can be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the second spacer material layer 1081 is silicon nitride.
[0132] The second spacer material layer 1081 may be formed using methods including but not limited to: chemical vapor deposition method and physical vapor deposition method.
[0133] Wherein, in the PMOS region, the second spacer material layer 1081 covers the surface of the first stressed epitaxial layer 106, is located on the first oxide layer 107, and is in the first fin structure 1011 in the PMOS region A second spacer material layer 1081 is formed on both the sidewalls of and the surface of the isolation structure 102.
[0134] Then, like Figure 8 As shown, a patterned second photoresist layer 1052 is formed to cover the PMOS region and expose the NMOS region. Using the patterned second photoresist layer 1052 as a mask, the second fin is etched away The first spacer material layer and the second spacer material layer on the top surface of the structure 1012 and on the surface of the semiconductor substrate 100 in the NMOS region are formed on the sidewalls of the second fin structure 1012 The first spacer 108 exposes part of the top surface of the second fin structure 1012.
[0135] Specifically, the patterned second photoresist layer 1052 is formed using a photolithography process (including processes such as coating photoresist, exposure and development), and the patterned second photoresist layer 1052 exposes the NMOS area The second spacer material layer.
[0136] Wherein, removing the first spacer material layer and the second spacer material layer on the surface of the semiconductor substrate 100 in the NMOS region, that is, removing the first gap on the surface of the isolation structure 102 in the NMOS region A wall material layer and the second spacer material layer.
[0137] The etching method may use any suitable dry etching or wet etching method well known to those skilled in the art, preferably, a dry etching method is used.
[0138] Exemplarily, the thickness of the first spacer 108 may range from 60 to 120 angstroms. The above thickness range is only an example, and other suitable ranges may also be applicable to the present invention.
[0139] Then, like Picture 9 As shown, with the patterned second photoresist layer 1052 as a mask, the exposed source/drain regions of the second fin structure 1012 are first etched back to remove part of the second fin structure 1012 forms a first groove 109.
[0140] In an example, the first etch-back also simultaneously removes the dummy gate dielectric layer 1031 on the sidewall of the second fin structure 1012.
[0141] The first etch back may use any suitable dry etching or wet etching or a combination thereof well known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. It is best to perform dry etching through one or more RIE steps.
[0142] After that, the patterned patterned second photoresist layer 1052 is removed. The patterned second photoresist layer 1052 can be removed using an ashing method.
[0143] Exemplarily, the depth range of the first etch-back is 20-40 nm, that is, the depth range of the etch-back downward from the top surface of the second fin structure 1012 is 20-40 nm, and this depth range is only an example.
[0144] Then, like Picture 10 As shown, the exposed surface of the second fin structure 1012 is oxidized to form a second oxide layer 110.
[0145] Specifically, the surface of the second fin structure 1012 exposed from the first groove 109 is oxidized to form the second oxide layer 110. The second oxide layer 110 serves as an etching stop layer when the first spacer is etched later.
[0146] The second oxide layer 110 made of silicon oxide may be formed by oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ water vapor oxidation (ISSG), etc.
[0147] Then, like Picture 11 As shown, the thickness of the first spacer 108 is reduced to expand the width of the first groove 109 to the first width L1.
[0148] Exemplarily, a wet etching method is used to achieve the thinning of the first spacer 108.
[0149] In an example, when the material of the first spacer 108 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve the thinning of the first spacer 108. It can also be a hot phosphoric acid solution, which has a high etching rate for silicon nitride and a low etching rate for oxides and the like.
[0150] Wherein, in this embodiment, after the first spacer 108 is thinned, the thickness of the remaining first spacer 108 ranges from 2 to 6 nm, but it is not limited to this.
[0151] It is worth mentioning that in the process of thinning the first spacer 108 by the wet etching, the second spacer material layer in the PMOS region is also etched and thinned.
[0152] Subsequently, the second oxide layer 110 is removed by pre-cleaning to expose the top surface of the second fin structure 1012 in the first groove 109. Exemplarily, the pre-cleaning can use a hydrofluoric acid solution, such as a buffer oxide etchant (BOE) or a buffer solution of hydrofluoric acid (BHF).
[0153] Then, like Picture 12 As shown, a second stressed epitaxial layer 111 is grown on the second fin structure 1012 exposed in the first groove 109 to fill the first groove, wherein the second stressed epitaxial layer 111 The width is the first width L1.
[0154] The second stress epitaxial layer 111 can be grown on the exposed surface of the second fin structure 1012 using a selective epitaxial growth method. The selective epitaxial growth can be low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), one of ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).
[0155] In NMOS, the second stressed epitaxial layer 111 usually has tensile stress. The material of the second stressed epitaxial layer 111 may be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stressed epitaxial layer. Specifically, a chemical vapor deposition method or a gas source molecular beam epitaxy method can be used to grow SiP, using silane or disilane as the silicon source, and phosphane as the phosphorus source.
[0156] Wherein, the top surface of the second stress epitaxial layer 111 can be higher than the top surface of the first spacer 108 on its sidewall. The first spacer 108 has a guiding effect on the growth of the second stress epitaxial layer 111 and controls its The first groove between the first spacers grows upward.
[0157] The exposed surface of the second stress epitaxial layer can also be selectively oxidized to form an oxide layer, which can be used as an etching stop layer when etching the spacer material layer later.
[0158] Then, like Figure 13 As shown, a third spacer material layer 1121 is deposited to cover the PMOS region and the NMOS region.
[0159] The third spacer material layer 1121 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the third spacer material layer 1121 is silicon nitride.
[0160] The third spacer material layer 1121 may be formed using methods including but not limited to: chemical vapor deposition method and physical vapor deposition method.
[0161] Then, like Figure 14 As shown, a patterned third photoresist layer 1053 is formed to cover the PMOS region and expose the NMOS region, and the patterned third photoresist layer 1053 is used as a mask to etch away the second stress A part of the third spacer material layer 1121 on the top surface of the epitaxial layer 111 and on the semiconductor substrate 100 in the NMOS region is used to form a gap between the second fin structure 1012 and the second stressed epitaxial layer 111 The second spacer 112 is formed on the side wall.
[0162] Specifically, the patterned third photoresist layer 1053 is formed using a photolithography process (including processes such as coating photoresist, exposure and development), and the patterned third photoresist layer 1053 exposes the NMOS area The third spacer material layer 1121.
[0163] Wherein, the third spacer material layer 1121 on the surface of the semiconductor substrate 100 in the NMOS region is removed, that is, the third spacer material layer 1121 on the surface of the isolation structure 102 in the NMOS region is removed.
[0164] The etching method may use any suitable dry etching or wet etching method well known to those skilled in the art, preferably, a dry etching method is used.
[0165] In an example, when an oxide is formed on the second stressed epitaxial layer 111, the oxide can also be removed to expose the top surface of the second stressed epitaxial layer 111.
[0166] Then, like Figure 15 As shown, using the patterned third photoresist layer 1053 as a mask, a second etch-back removes part of the second stressed epitaxial layer 111 to form a second groove 113.
[0167] The second etching back can use any suitable dry etching or wet etching or a combination thereof well known to those skilled in the art. Preferably, an anisotropic dry etching method is used, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. It is best to perform dry etching through one or more RIE steps.
[0168] Exemplarily, the wet etching may use an etching method having a high etching rate for the second stress epitaxial layer 111 and a low etching rate for the spacers and the isolation structure.
[0169] Exemplarily, the depth range of the second etch-back is 10-20 nm, that is, the depth range of the etch-back from the top surface of the second stressed epitaxial layer is 10-20 nm, and this depth range is only an example.
[0170] After that, the patterned patterned third photoresist layer 1053 is removed. The patterned third photoresist layer 1053 can be removed using an ashing method.
[0171] Then, like Figure 16 As shown, the thickness of the second spacer 112 is reduced to expand the width of the second groove 113 to the second width L2.
[0172] Exemplarily, a wet etching method is used to achieve the thinning of the second spacer 112.
[0173] In an example, when the material of the second spacer 112 is silicon nitride, the wet etching may use an etchant including phosphoric acid to achieve the thinning of the second spacer 112. It can also be a hot phosphoric acid solution, which has a high etching rate for silicon nitride and a low etching rate for oxides and the like.
[0174] Wherein, in this embodiment, after the second spacer 112 is thinned, the thickness of the remaining second spacer 112 ranges from 2 to 6 nm, but it is not limited to this.
[0175] It is worth mentioning that during the process of thinning the second spacer 1128 by the wet etching, the third spacer material layer 1121 in the PMOS region is also etched and thinned.
[0176] Then, like Figure 17 As shown, a third stressed epitaxial layer 114 is grown on the surface of the second stressed epitaxial layer 111 to fill the second groove and overflow to the top surface of the remaining second spacer 112, wherein , The width of the third stressed epitaxial layer 112 in the second groove is the second width L2, and the third stressed epitaxial layer 114 located above the top surface of the second spacer 112 has a third The width L3, wherein the first width L1 is smaller than the second width L2, and the second width L2 is smaller than the third width L3.
[0177] It is worth mentioning that the first width, the second width, and the third width mean that the second stress epitaxial layer and the second stress epitaxial layer are cut by a plane perpendicular to the surface of the semiconductor substrate and perpendicular to the extension direction of the fin structure. The width of the corresponding section obtained by the third stress epitaxial layer.
[0178] The third stressed epitaxial layer 114 can be grown on the exposed surface of the second stressed epitaxial layer 111 using a selective epitaxial growth method. The selective epitaxial growth can adopt low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) ), one of ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).
[0179] In NMOS, the third stressed epitaxial layer 114 usually has tensile stress. The material of the third stressed epitaxial layer 114 may be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the third stressed epitaxial layer 114. Specifically, a chemical vapor deposition method or a gas source molecular beam epitaxy method can be used to grow SiP, using silane or disilane as the silicon source, and phosphane as the phosphorus source.
[0180] Wherein, when the third stress epitaxial layer 114 is epitaxially grown, the second spacer 112 has a guiding function for the growth of the third stress epitaxial layer 114, controlling its growth upward in the second groove between the second spacer 112 .
[0181] Through the above method, a SiP stressed epitaxial layer is formed in the source/drain area of the NMOS area. The stressed epitaxial layer includes a second stressed epitaxial layer with a first width at the bottom and a third stressed epitaxial layer on the second stressed epitaxial layer. Epitaxial layer, wherein the third stressed epitaxial layer includes from bottom to top a third stressed epitaxial layer with a second width and a third stressed epitaxial layer with a third width above the top surface of the second spacer, wherein the first width is smaller than the first The second width is smaller than the third width, so the top of the stressed epitaxial layer is enlarged and the contact area is larger, so that the stressed epitaxial layer has a lower external resistance. Furthermore, since the bottom of the stressed epitaxial layer is not increased The volume, so that the short channel effect has also been well controlled.
[0182] Then, like Figure 18 As shown, a contact hole etch stop layer 115 is formed on the surface of the semiconductor substrate 100, the first stressed epitaxial layer 106, the third stressed epitaxial layer 114, and the second spacer 112; An interlayer dielectric layer 116 is deposited on the contact hole etch stop layer 115, and the interlayer dielectric layer 116 is planarized.
[0183] A contact hole etch stop layer (CESL) 115 is formed on the substrate. The contact hole etch stop layer may include a dielectric material, such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like.
[0184] The contact hole etch stop layer 115 may include any two of several etch stop materials. Non-limiting examples include conductor etch stop materials, semiconductor etch stop materials, and dielectric etch stop materials. For reasons that will become more obvious in the additional description below, the etch stop layer includes an etch stop material that is susceptible to local changes, which provides the etch stop layer with area-specific etch selectivity. In the present invention, the contact hole etching stop layer 115 is composed of two layers, an oxide layer included and a nitride layer outside the oxide layer, wherein the oxide can be SiO 2 The nitride can be selected from one of SiCN, SiN, SiC, SiOF, SiON, but the contact hole etching stop layer is not limited to the above examples.
[0185] The interlayer dielectric layer 116 is then deposited and planarized. Non-limiting examples of the planarization treatment include a mechanical planarization method and a chemical mechanical polishing (CMP) planarization method.
[0186] The interlayer dielectric layer 116 may be a silicon oxide layer, including a doped or undoped silicon oxide material layer formed by a thermal CVD (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, For example, undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus or boron doped Tetraethoxysilane (BTEOS).
[0187] So far, the introduction of the main steps of the manufacturing method of the semiconductor device of the present invention is completed. For the production of the complete device, other preceding steps, intermediate steps or subsequent steps are required, which will not be repeated here.
[0188] According to the manufacturing method of the present invention, spacers are used as a guide when the stress epitaxy layer is grown in the source/drain regions of the NMOS region. Therefore, a merged epitaxy is not formed. In addition, the top of the stress epitaxy is enlarged to make contact The area is larger, so the stressed epitaxial layer has lower external resistance. Moreover, since the volume of the bottom stressed epitaxial layer is not basically increased, the short channel effect is also well controlled. Therefore, according to the present invention The manufacturing method reasonably balances the volume and profile of the source/drain stress epitaxial layer, and improves the performance and yield of the device.
Example Embodiment
[0189] Example two
[0190] The present invention also provides a semiconductor device prepared by using the method in the first embodiment.
[0191] Specifically, such as Figure 17 with Figure 18 As shown, the semiconductor device of the present invention includes a semiconductor substrate 100. The semiconductor substrate 100 includes a PMOS region and an NMOS region. A first fin structure is formed on the semiconductor substrate 100 in the PMOS region and the NMOS region. 1011 and a second fin structure 1012.
[0192] Specifically, the semiconductor substrate 100 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, as well as these semiconductor components. Multi-layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI) Wait. In this embodiment, the semiconductor substrate 100 is preferably a silicon substrate.
[0193] A first fin structure 1011 is formed on the semiconductor substrate 100 in the PMOS region, and a second fin structure 1012 is formed on the semiconductor substrate 100 in each NMOS region.
[0194] In an example, the method of forming the first fin structure 1011 and the second fin structure 1012 includes the following steps:
[0195] A patterned mask layer is formed on the surface of the semiconductor substrate 100, and the patterned mask layer defines patterns of the first fin structure 1011 and the second fin structure 1012, including fins Using the patterned mask layer as a mask, the semiconductor substrate 100 is etched to form the first fin structure 1011 and the second fin structure 1012. The mask layer may generally include any one of several mask materials, including but not limited to: hard mask materials and photoresist mask materials. The above-mentioned etching can be performed by a method such as dry etching or wet etching, wherein the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may be used, or more than one etching method may be used.
[0196] It should be noted that the method of forming the first fin structure 1011 and the second fin structure 1012 is only exemplary, and is not limited to the above method.
[0197] The widths of the fin structures are all the same, or the fins are divided into multiple fin structure groups with different widths, and the length of the fin structures may also be different.
[0198] An isolation structure 102 is also formed on the semiconductor substrate 100. The isolation structure 102 may be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. In this embodiment, the isolation structure 102 is preferably shallow. Trench isolation structure. The top surface of the isolation structure 102 is lower than the top surfaces of the first fin structure 1011 and the second fin structure 1012. Various well structures are also formed in the semiconductor substrate 100. For example, an N-type well is formed in the PMOS region, and a P-type well is formed in the NMOS region. For simplicity, the illustration is omitted.
[0199] Further, a first gate structure and a second gate structure spanning part of the first fin structure 1011 and part of the second fin structure 1012 are formed in the PMOS region and the NMOS region, respectively.
[0200] Both the first gate structure and the second gate structure include a bottom-up gate dielectric layer 1031 and a gate layer 1032.
[0201] Gate dielectric layer 1031 The gate dielectric layer may be formed by thermal oxidation, nitridation or oxynitridation processes. When forming the gate dielectric layer, the above processes can also be used in combination. The gate dielectric layer can include any of the following conventional dielectrics: SiO 2 , Si 3 N 4 , SiON, SiON 2 , Such as TiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 , La 2 O 3 And other similar oxides including perovskite-type oxides, but not limited to this. Generally, high-k dielectrics can withstand high temperature (900°C) annealing. The gate dielectric layer may also include any combination of the aforementioned dielectric materials.
[0202] The gate layer 1032 is formed on the gate dielectric layer 1031. In one embodiment, the gate layer is made of polysilicon material. Generally, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer.
[0203] In an example, a first stressed epitaxial layer 106 is formed in the source/drain regions of the first fin structure 1011 on both sides of the first gate structure, and a first stressed epitaxial layer 106 is also formed on the surface of the first stressed epitaxial layer 106 The first oxide layer 107 has spacer material formed on the surface of the first oxide layer 107, on the sidewalls of the first fin structure 1011, and on the surface of the semiconductor substrate 100 in the PMOS region 层1121.
[0204] The material of the first stressed epitaxial layer 106 may include SiGe or other suitable materials that can provide compressive stress.
[0205] A stress layer with compressive stress is formed in the PMOS, and the performance of the CMOS device can be improved by applying compressive stress to the PMOS.
[0206] Among them, preferably, the cross-sectional shape of the first stress epitaxial layer 106 is preferably a "Σ" shape.
[0207] Illustratively, the first oxide layer 107 is silicon oxide formed using an oxidation treatment method.
[0208] The spacer material layer 1121 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation of this embodiment, the spacer material layer 1121 is silicon nitride.
[0209] Further, the semiconductor device of the present invention further includes a second stress epitaxy with a first width L1 formed from bottom to top in the source/drain regions of the second fin structure 1012 on both sides of the second gate structure. Layer 111, the third stressed epitaxial layer 114 of the second width L2, and the third stressed epitaxial layer 114 of the third width L3, wherein the first width L1 is smaller than the second width L2, and the second width L2 is smaller than the third width L3, and spacers 112 are formed on the sidewalls of the second fin structure 1012, the second stressed epitaxial layer 111, and the third stressed epitaxial layer 114 of the second width.
[0210] The spacer 112 may be one of silicon oxide, silicon nitride, and silicon oxynitride or a combination thereof. As an implementation of this embodiment, the spacer 112 is silicon nitride.
[0211] In NMOS, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 generally have tensile stress. The material of the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may be SiP, SiC or other suitable materials that can provide tensile stress. In this embodiment, SiP is preferably selected as the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114. Specifically, a chemical vapor deposition method or a gas source molecular beam epitaxy method can be used to grow SiP, using silane or disilane as the silicon source, and phosphane as the phosphorus source.
[0212] Exemplarily, the second stressed epitaxial layer 111 and the third stressed epitaxial layer 114 may also be different materials with tensile stress.
[0213] In the semiconductor device of the present invention, an SiP stressed epitaxial layer is formed in the source/drain area of the NMOS area. The stressed epitaxial layer includes a second stressed epitaxial layer with a first width at the bottom, and a stress epitaxial layer on the second stressed epitaxial layer. The third stressed epitaxial layer, wherein the third stressed epitaxial layer includes from bottom to top a third stressed epitaxial layer with a second width and a third stressed epitaxial layer with a third width above the top surface of the second spacer, wherein the first The width is smaller than the second width, and the second width is smaller than the third width. Therefore, the top of the stressed epitaxial layer is enlarged and the contact area is larger. Therefore, the stressed epitaxial layer has a lower external resistance. Furthermore, since the bottom stress is not increased The volume of the epitaxial layer enables the short channel effect to be well controlled.
[0214] Further, a contact hole etch stop layer 115 is formed on the surface of the semiconductor substrate 100, the first stressed epitaxial layer 106, the third stressed epitaxial layer 114, and the spacer 112; An interlayer dielectric layer 116 is deposited on the hole etch stop layer 115.
[0215] A contact hole etch stop layer (CESL) 115 is formed on the substrate. The contact hole etch stop layer may include a dielectric material, such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like.
[0216] The contact hole etch stop layer 115 may include any two of several etch stop materials. Non-limiting examples include conductor etch stop materials, semiconductor etch stop materials, and dielectric etch stop materials. For reasons that will become more obvious in the additional description below, the etch stop layer includes an etch stop material that is susceptible to local changes, which provides the etch stop layer with area-specific etch selectivity. In the present invention, the contact hole etching stop layer 115 is composed of two layers, an oxide layer included and a nitride layer outside the oxide layer, wherein the oxide can be SiO 2 The nitride can be selected from one of SiCN, SiN, SiC, SiOF, SiON, but the contact hole etching stop layer is not limited to the above examples.
[0217] The interlayer dielectric layer 116 may be a silicon oxide layer, including a doped or undoped silicon oxide material layer formed by a thermal CVD (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, For example, undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus or boron doped Tetraethoxysilane (BTEOS).
[0218] For a complete device, it also includes other structural components, which are not described here.
[0219] Since the semiconductor device of the present invention is prepared by the aforementioned method, it has the same advantages.
[0220] The semiconductor device of the present invention uses spacers as a guide when growing the stress epitaxy layer in the source/drain regions of the NMOS region, and therefore does not form a merged epitaxy. In addition, since the semiconductor device of the present invention includes an enlarged stress epitaxy The top of the layer makes the contact area larger, so the stressed epitaxial layer has lower external resistance. Moreover, since the volume of the bottom stressed epitaxial layer is basically not increased, the short channel effect is also well controlled. The volume and profile of the source/drain stress epitaxial layer are reasonably balanced. Therefore, the performance of the semiconductor device according to the present invention is higher.
Example Embodiment
[0221] Example three
[0222] The present invention also provides an electronic device, including the semiconductor device described in the second embodiment, and the semiconductor device is manufactured according to the method described in the first embodiment.
[0223] The electronic device of this embodiment may be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV, a VCD, a DVD, a navigator, a digital photo frame, a camera, a camcorder, a voice recorder, MP3, MP4, PSP, etc. Products or equipment can also be any intermediate products that include circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.
[0224] among them, Picture 20 An example of a mobile phone handset is shown. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.
[0225] The mobile phone handset includes the semiconductor device described in the second embodiment, and the semiconductor device mainly includes:
[0226] A semiconductor substrate, the semiconductor substrate includes a PMOS region and an NMOS region, and a first fin structure and a second fin structure are respectively formed on the semiconductor substrate in the PMOS region and the NMOS region;
[0227] A first gate structure and a second gate structure spanning part of the first fin structure and part of the second fin structure are respectively formed in the PMOS region and the NMOS region;
[0228] A first stress epitaxial layer is formed in the source/drain regions of the first fin structure on both sides of the first gate structure;
[0229] A second stress epitaxial layer of a first width, a third stress epitaxial layer of a second width, and a second stress epitaxial layer of a second width are formed from bottom to top in the source and drain regions of the second fin structure on both sides of the second gate structure The third stress epitaxial layer with three widths, wherein the first width is smaller than the second width, and the second width is smaller than the third width;
[0230] Spacers are formed on the sidewalls of the second fin structure, the second stressed epitaxial layer, and the third stressed epitaxial layer of the second width.
[0231] The electronic device of the present invention includes the aforementioned semiconductor device and therefore also has the same advantages.
PUM
| Property | Measurement | Unit |
| Thickness | 60.0 ~ 120.0 | Å |
| Thickness | 2.0 ~ 6.0 | nm |
Description & Claims & Application Information
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