GaN transistor covered with nanopillar barrier and preparation method thereof

Abstract

The invention discloses a GaN transistor covered with a nanopillar barrier and a preparation method thereof. AlxGa1-xN alloy nanopillars are distributed on the surface of the barrier layer of a transistor and correspond to screw dislocations in the barrier layer one to one. The method, by controlling the TMGa flow rate and the V / III ratio during the growth of AlxGa1-xN barrier, not only can avoidthe formation of V-shaped defects at the termination of screw dislocations, but also can form 1-3 nm AlxGa1-xN alloy nanopillars at the termination of screw dislocations. As the alloy nanopillars fillthe V-shaped defects at the termination of screw dislocations on the barrier surface and increase the effective barrier thickness at the termination of the screw dislocations, the gate leakage current is suppressed and the withstand voltage characteristic of the transistor is improved.

Description

technical field [0001] The invention relates to the growth of semiconductor materials and the manufacture of semiconductor devices, in particular to a GaN-based transistor covered with nanocolumns and a barrier growth method thereof. Background technique [0002] GaN-based high electron mobility transistors (HEMTs) are made of Al x Ga 1-x N and GaN form a heterojunction, Al x Ga 1-x The interface spontaneous polarization and piezoelectric polarization discontinuity of the N / GaN heterojunction form remnant polarization charges, thereby forming a high-concentration two-dimensional electron gas at the interface. High quality Al x Ga 1-x The growth technology of the N barrier layer is one of the key epitaxial technologies for GaN-based transistors. GaN-based HEMTs have the advantages of high two-dimensional electron gas (2DEG) concentration, high mobility, and strong breakdown electric field, and are widely used in high-frequency and high-voltage microwave devices. [000...

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Problems solved by technology

[0004] In order to reduce the impact of screw dislocation defects on device performance, it is generally grown on a SiC substrate with a small lattice mismatch, using a complex buffer layer structure, and using a lateral epitaxial growth method to filter threading dislocations to reduce the potential barrier. The screw dislocation density of the layer and other methods, the above-mentioned method is high in cost, complicated in process and poor in controllability

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