Automatic chip simulation and verification system

Abstract

The invention discloses an automatic chip simulation and verification system. The system comprises a chip system model, wherein the chip system model corresponds to a system-on-chip chip; a hardware model and a software model corresponding to the system-on-chip chip is established in the chip system model; the chip system model is used for randomly generating a plurality of groups of test vectorsand operating a test program; the test program is divided into a plurality of stages according to design and staged test results of the test are stored to units areas of a predetermined area; a simulator communicates with the chip system model; a simulation program of the simulator is divided into a plurality of simulation stages; staged simulation results of the simulation program are stored intounit areas of the predetermined area; and the chip system model is furthermore used for comparing the test results with the simulation results. According to the automatic chip simulation and verification system and method, automatic realization of the whole simulation and verification process is realized, so that the efficiency is relatively high; and the operation of constructing the chip systemmodel by utilizing abstract-level languages which comprise a hardware description language is relatively simple.

Description

technical field [0001] The invention relates to the technical field of detection of chip products, in particular to a chip automatic simulation verification system. Background technique [0002] System On Chip (System On Chip, SOC) refers to the integration of all functional systems required for microelectronic application products on a single chip, which is based on Very Deep Submicron (VDSM) technology and intellectual property (Intellectual Property, IP ) nuclear multiplexing technology as the support. SOC technology is the current development trend of Very Large Scale Integrate (VLSI), and it is also the main technology and method to solve Time to Market (TTM) in the development of electronic products. [0003] With the rapid development of deep submicron technology, the integration scale of chips is getting larger and larger, and the verification of chip functions has become more and more important and complex and time-consuming, and the design methods of chips have al...

AI Technical Summary

Problems solved by technology

However, the traditional chip simulation verification takes a long time, the degree of automation is low, and it is time-consuming and laborious, which leads to a longer development cycle of the entire chip.

[0004] The traditional verification test mode is open-loop, requiring special personnel to manage and control input test vectors and observe simulation waveforms, which is time-consuming and labor-intensive

[0005] However, some automatic simulation platforms, such as PLI automatic simulation platform, also have various problems. 1) The PLI standard is complicated to use; 2) PLI must define system tasks or functions, and associate the calltf C function with the system task / function name; 3) The communication protocol interaction between the C model and the circuit is complex

This results in a high barrier to entry for using these automated emulation platforms

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