Semiconductor transistor preparation method and structure

Abstract

The invention discloses a semiconductor transistor preparation method and structure. The structure comprises a semiconductor substrate; a gate structure arranged on the upper surface of the semiconductor substrate and comprising a gate conductive layer and a gate insulation layer arranged on the gate conductive layer; gate insulation side walls arranged at the side walls of the gate structure; bolt conductive structures arranged at the two sides of the gate structure, wherein the bolt conductive structures are electrically isolated through an air insulation structure or an insulation layer; and air side walls arranged between bolt conductive layers and the gate insulation side walls. Each air side wall comprises an air gap and an insulated seal layer, wherein the air gap is sealed by the insulated seal layer. Compared with the prior art, through introduction of the air gaps and air gap chambers, not only parasitic capacitance between grid electrodes and the bolt conductive structures is reduced, but also parasitic capacitance between the bolt conductive structure and the bolt conductive structure is reduced, thereby improving stability and reliability of a transistor, and providingan effective means for further reducing the size of the transistor.

Description

technical field [0001] The invention relates to a manufacturing process of a semiconductor device, in particular to a manufacturing method and structure of a semiconductor transistor. Background technique [0002] A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) is the most commonly used unit in an integrated circuit. Since the voltages of the gate, source and drain of the MOSFET are not equal under normal working conditions, there is a coupling effect in the electric field between them, and this coupling effect is manifested as the existence of capacitance between them. With the development of integrated circuits, the miniaturization of devices is an inevitable trend, but the parasitic capacitance in the process does not decrease proportionally with the reduction of device size, while the intrinsic capacitance decreases proportionally with the reduction of device size , so that the proportion of parasitic capac...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method and structure for the preparation of a semiconductor transistor, which is used to solve the problems between the gate and the plug conductive structure, as well as the plug conductive structure and the plug conductive structure in the prior art. The problem of large parasitic capacitance between, improve device stability and reliability

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