Metal oxide semiconductor device with double well and its manufacturing method

Abstract

The invention proposes a metal oxide semiconductor (MOS) component with dual wells and a manufacturing method of the MOS component. The MOS component with dual wells comprises a semiconductor substrate, an action layer, a first conductive type of well, a first conductive type of body region, a second conductive type of well, a grid, a second conductive type of light-doping diffusion region, a second conductive type of source, a second conductive type of connection region and a second conductive type of drain, wherein the second conductive type of well is adjacent to the first conductive type of well and is formed on a PN connection surface formed right below the gird, the second conductive type of connection region is longitudinally arranged right below an interlayer between the grids andis horizontally connected to the second conductive type of source so as to prevent the condition that a passage is not conducted during conduction operation of the MOS component, the second conductivetype of connection region has an acceleration ion beam with an inclination angle and is formed by an ion implantation process penetrating the interlayer.

Description

technical field [0001] The present invention relates to a metal oxide semiconductor (MOS) element with double wells and a manufacturing method thereof, in particular to a MOS element capable of reducing on-resistance and increasing breakdown protection voltage and a manufacturing method thereof. Background technique [0002] figure 1 A schematic cross-sectional view of a typical metal oxide semiconductor (MOS) device 100 is shown. Such as figure 1 As shown, the MOS device 100 includes: a P-type substrate 101, an active layer 102, a P-type well 103, an isolation oxide region 104, an N-type lightly doped diffusion (LDD) region 105a and 105b, and an N-type source 106 , N-type drain 107 , P-type body region 108 , and gate 111 . Wherein, the isolation oxidation region 104 is a local oxidation of silicon (LOCOS) structure to define an operation region 104 a as a main active region when the MOS device 100 operates. The scope of the operating area 104a is defined by figure 1 , ...

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Problems solved by technology

[0003] Generally speaking, taking a MOS device with a gate operating voltage of 5V as an example, when the channel length indicated by the gate length is below 0.6 microns (μm), SCE will begin to appear. To avoid SCE, the gate length must not Continue to shorten, of course there are many other ways to solve this SCE, but if you need to keep the operating voltage at about 5V, such as integrating with other power components in a circuit, or using multiple MOS components in parallel as power components, It is necessary to solve the problem of maintaining the gate operating voltage at, for example, about 5V, and avoiding SCE, so that the MOS device can continue to shrink

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