Fully differential switch capacitor integrator

Abstract

The invention provides a fully differential switch capacitor integrator. The fully differential switch capacitor integrator comprises an operational amplifier unit, a switch capacitor unit, a switch capacitor common-mode feedback unit, and a non-overlapping clock production unit, wherein the operational amplifier unit comprises an operational amplifier for providing predetermined gain and bandwidth; the switch capacitor unit comprises a switch capacitor integral unit bridged between the input end and output end of the operational amplifier, a serial branch comprising a MOS switch phi2 and a capacitor C1, wherein the capacitor C3 is connected with the above branch in parallel, and a MOS switch phi1 is further arranged between the MOS tube phi2 and the capacitor C1 to connect to a referencevoltage Vref, and partial positive feedback capacitor C2 connected to the output end of the opposite polarity of the operational amplifier; the switch capacitor common-mode feedback unit is arranged between the positive output end and the negative output end of the operational amplifier, and is a six-switch four-capacitor structure; the non-overlapping clock production unit produces a clock signalof the MOS switch. The fully differential switch capacitor integrator provided by the invention is insensitive to parasitic, and has efficient area utilization rate and greater time constant.

Description

technical field [0001] The present disclosure relates to a switched capacitor integrator, in particular to a fully differential switched capacitor integrator suitable for the field of biomedical electronics requiring large time constant filters, such as ECG monitoring, EEG monitoring and other signal acquisition circuits. Background technique [0002] In electrophysiological signal monitoring circuits such as ECG and EEG, in order to collect electrophysiological signals ranging from tens of microvolts to several millivolts, the front-end amplifier usually has an amplification factor of about 100 times to reduce the equivalent input noise of subsequent circuits. It is divided into AC coupling type and DC coupling type. In order to avoid the DC offset of tens to hundreds of millivolts of the electrode from saturating the amplifier, and to ensure that the signal above 0.1Hz to 0.5Hz can be collected, the AC coupling type uses a large capacitor to block DC. , The DC-coupled type...

AI Technical Summary

Problems solved by technology

[0005] In addition, there is an OTA-C structure or a digital processing circuit to increase the time constant of the integrator, which is more complex

[0006] To sum up, in the case of obtaining a large time constant, ease of design, and high precision, the fully differential switched capacitor integrator has obvious advantages, but to continue to increase its time constant, only increase the capacitor C3 or Reducing capacitors C0 and C1, increasing C3 will increase the chip area, reducing C0 and C1 will make the charge injection and clock feedthrough effects of MOS switches relatively worse, and the influence of parasitic capacitance of metal traces in the layout will also be relatively reduced. Big

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