Semiconductor structures and methods of forming them

Abstract

Disclosed are a semiconductor structure and a formation method thereof. The formation method comprises the steps: a semiconductor substrate is provided, wherein a gate structure is arranged on the semiconductor substrate; source drain doping regions are formed in the semiconductor substrate on the two sides of the gate structure; a first stop layer is on the top surface of the gate structure; a second stop layer is on the surfaces of the source drain doping regions; an interlayer dielectric layer is arranged on the semiconductor substrate, the source drain doping regions and the gate structure; the interlayer dielectric layer is positioned on the surfaces of the first stop layer and the second stop layer; a first opening for exposing the first stop layer is formed in the interlayer dielectric layer; a second opening for exposing the second stop layer is formed in the interlayer dielectric layer; the first stop layer at the bottom of the first opening is removed to form a first contacthole; the second stop layer at the bottom of the second opening is removed to form a second contact hole; and conductive plugs are formed in the first contact hole and the second contact hole. The formed semiconductor structure is relatively low in contact resistance and relatively high in performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the field of semiconductor technology, the manufacture of semiconductor integrated circuits is an extremely complex process, the purpose of which is to reduce the electronic components and circuits required for a specific circuit on a small-area wafer. Among them, the various components must be electrically connected through appropriate interconnecting wires in order to perform expected functions. [0003] As the manufacturing of integrated circuits develops towards VLSI, the internal circuit density is getting larger and larger. As the number of components contained in the chip continues to increase, the available space for surface wiring is actually reduced. One solution to this problem is to adopt a multi-layer metal wire design, using multi-layer connections in which multiple l...

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Problems solved by technology

[0005] However, the contact resistance of the conductive plug formed by the existing technology is relatively large, and the performance of the semiconductor structure is poor.

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