flash memory

Abstract

The invention discloses a flash memory. In a flash memory unit array, active regions isolated by a field oxide layer are included on the surface of a semiconductor substrate, each active region is in a strip structure and arranged in parallel, and a polysilicon floating gate is located in the active region. and isolated by the first gate oxide. In the width direction of the active region, under the condition that the sides of the polysilicon floating gate and the corresponding sides of the active region are photolithographically aligned, the width expansion of the polysilicon floating gate caused by the field oxide layer being etched and consumed will be formed. The two sides of the polysilicon floating gate are provided with a convex-concave structure, and the convex and concave parts of the convex-concave structure are arranged in correspondence with each other so that the side spacing of the polysilicon floating gate is expanded. The invention can reduce the mutual interference between adjacent polysilicon floating gates, which is beneficial to increase the drain voltage and improve the programming speed; it can also increase the coupling rate between the control gate and the floating gate, which is beneficial to further reduce the gate voltage; It is beneficial to further reduce the size of the flash memory unit.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a flash memory (Flash). Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. The feature size of high-node technology is smaller, so it can improve the integration of flash memory. At the same time, the maturity of new technology nodes also promotes the production of flash memory cells at high nodes. [0003] In the existing process, theoretically, the width side of the polysilicon floating gate is usually self-aligned with the edge of the active region, but in practice, the width side o...

AI Technical Summary

Problems solved by technology

However, with the application of high-node technology, the situation that the width of the polysilicon floating gate is greater than the width of the active area will bring greater adverse effects, especially in the scaling down of the size, which usually affects the active area and field oxidation. The width of the layer is reduced proportionally, and the size of the pad oxide layer will not change, so the consumption of the field oxide layer caused by the etching of the pad oxide layer will change the size of the active region and occupy the width of the active region The ratio will gradually increase

The situation that the width of the polysilicon floating gate is greater than the width of the active region will make the spacing between the polysilicon floating gates smaller than the spacing between the active regions, and the reduction of the polysilicon floating gate spacing will increase the mutual interference between the polysilicon floating gates, Lead to stored information errors, and the pitch of polysilicon floating gates will decrease sharply as the size of technology nodes shrinks

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