Unlock instant, AI-driven research and patent intelligence for your innovation.

Uncooled infrared detector chip as well as packaging structure and preparation method thereof

A packaging structure and chip technology, applied in the direction of semiconductor devices, final product manufacturing, sustainable manufacturing/processing, etc., can solve problems such as waste of cost, complicated process, and detector damage, and achieve flexible switching, reduced packaging area, and reduced small area effect

Active Publication Date: 2018-08-10
WUHAN GAOXIN TECH
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this technology uses pad bonding technology to package, which will cause damage to temperature-sensitive detectors, and the use of wire bonding technology, the package area is larger than the chip area, wasting costs, and the electrical connection is complicated to implement.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Uncooled infrared detector chip as well as packaging structure and preparation method thereof
  • Uncooled infrared detector chip as well as packaging structure and preparation method thereof
  • Uncooled infrared detector chip as well as packaging structure and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] S1: Etching criss-cross dicing grooves 3 on the upper surface of the wafer 1 to obtain a grid-like chip array, each of the grids of the chip array is a chip body 2-1, on the wafer 1 growing a sacrificial material on the upper surface of the circle 1, filling the scribe groove 3 and covering the chip main body 2-1, obtaining a sacrificial layer 2-2 on the upper surface of each chip main body 2-1;

[0053] S2: respectively etch the upper surface of the left and right ends of each sacrificial layer 2-2 to obtain a groove 2-31, etch the chip body 2-1 downward along the groove 2-31 to obtain a connected chip body 2- 1 and the circuit external connection slot 2-3 of the sacrificial layer 2-2;

[0054] S3: Etch the sacrificial material in the scribe groove 3 laterally along the circuit external groove 2-3 to obtain a connecting groove connecting two adjacent circuit external grooves 2-3, and etch the connecting groove downward to the scribed groove Fill the bottom of the chip...

Embodiment 2

[0060] S1: Etching criss-cross dicing grooves 3 on the upper surface of the wafer 1 to obtain a grid-like chip array, each of the grids of the chip array is a chip body 2-1, on the wafer 1 growing a sacrificial material on the upper surface of the circle 1, filling the scribe groove 3 and covering the chip main body 2-1, obtaining a sacrificial layer 2-2 on the upper surface of each chip main body 2-1;

[0061] S2: respectively etch the upper surface of the left and right ends of each sacrificial layer 2-2 to obtain a groove 2-31, etch the chip body 2-1 downward along the groove 2-31 to obtain a connected chip body 2- 1 and the circuit external connection slot 2-3 of the sacrificial layer 2-2;

[0062] S3: Etch the sacrificial material in the scribe groove 3 laterally along the circuit external groove 2-3 to obtain a connecting groove connecting two adjacent circuit external grooves 2-3, and etch the connecting groove downward to the scribed groove Fill the bottom of the chip...

Embodiment 3

[0069] S1: Etching criss-cross dicing grooves 3 on the upper surface of the wafer 1 to obtain a grid-like chip array, each of the grids of the chip array is a chip body 2-1, on the wafer 1 growing a sacrificial material on the upper surface of the circle 1, filling the scribe groove 3 and covering the chip main body 2-1, obtaining a sacrificial layer 2-2 on the upper surface of each chip main body 2-1;

[0070] S2: respectively etch the upper surface of the left and right ends of each sacrificial layer 2-2 to obtain a groove 2-31, etch the chip body 2-1 downward along the groove 2-31 to obtain a connected chip body 2- 1 and the circuit external connection slot 2-3 of the sacrificial layer 2-2;

[0071] S3: Etch the sacrificial material in the scribe groove 3 laterally along the circuit external groove 2-3 to obtain a connecting groove connecting two adjacent circuit external grooves 2-3, and etch the connecting groove downward to the scribed groove Fill the bottom of the chip...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a chip prepared through an MEMS (Micro-Electro-Mechanical system) process and a packaging structure of the chip. A sacrificial layer grows on a chip main body; the sacrificiallayer is etched by using the MEMS process and is injected with a metal, so that a PAD (a circuit external point on the chip) is transferred to the side wall of the chip; meanwhile, a metal is injectedinto a corresponding position in a scribing slot to connect the PAD on the side wall of an adjacent chip, so that the PAD on the side wall can be led to the bottom end of the side wall; and the scribing slot is cut to obtain a single chip provided with the PAD on the side wall. The chips obtained by the method are directly laminated up and down to complete electric connection, and a single packaging clamping slot can be used for integration; furthermore, the packaging structure is applicable to chip scale packaging, wafer scale packaging and picture element scale packaging; a packaging routing process is eliminated; a chip packaging area is reduced; the chip is high in integration degree; process steps are simplified; batch production can be realized; and the cost is further reduced.

Description

technical field [0001] The invention belongs to the field of chip processing, and more specifically relates to an uncooled infrared detector chip and its packaging structure and preparation method. Background technique [0002] Infrared focal plane detector is the core component of the thermal imaging system and the key to detecting, identifying and analyzing the infrared information of objects. It has a wide range of applications in military, industry, transportation, security monitoring, meteorology, medicine and other industries. In recent years, the array size of uncooled infrared focal plane detectors has been increasing, and the pixel size has been decreasing. In addition, the detector unit structure and its optimization design, chip body design, packaging form and other aspects require continuous innovation and development of new technologies. [0003] The temperature change of the microbolometer of the infrared focal plane detector is very weak after receiving the in...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/02H01L31/18
CPCH01L31/02002H01L31/18Y02P70/50
Inventor 蔡光艳马占锋高健飞黄立
Owner WUHAN GAOXIN TECH