A kind of igbt chip with compound gate structure containing dummy gate
A composite gate and chip technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., to achieve the effect of shielding mutual interference, retaining low pass consumption, and optimizing input and output capacitance
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0043] Figure 4 It is a schematic plan view of the hexagonal cell of the IGBT chip with the composite gate structure including the dummy gate in the first embodiment of the present invention. Such as Figure 4 As shown, each cell 410 is a hexagonal cell structure, and a plurality of cells are distributed on the wafer substrate in a honeycomb shape. Wherein, each cell 410 includes a gate region 401 and trench gate active regions 402 and planar gate active regions 403 located on both sides of the gate region 401 .
[0044] for more clarity Figure 4 The structure of the IGBT chip shown below is Figure 4 The cell cross-sectional view of the shown IGBT chip along the A-A' direction is taken as an example for detailed description.
[0045] Figure 5 It is a cell cross-sectional view of the IGBT chip along the A-A' direction in the first embodiment of the present invention. Such as Figure 5 As shown, a cell mainly includes two mirror-symmetric composite gate units. becaus...
no. 2 example
[0063] The difference between this embodiment and the first embodiment is that the planar gate is also connected to the second trench gate (ie, the dummy gate).
[0064] Figure 8 It is a cell cross-sectional view along the A-A' direction of an IGBT chip with a composite gate structure including a dummy gate in the second embodiment of the present invention. Such as Figure 8 as shown, Figure 8 The gate oxide layer 804 with Figure 5 The gate oxide layer 504 is set differently.
[0065]Specifically, the gate oxide layer 804 isolates the first trench gate 501 , the second trench gate 502 and the planar gate 503 from the wafer substrate. The polysilicon of the planar gate 503 and the polysilicon of the first trench gate 501 are connected together to serve as the folded gate of the composite gate unit. The polysilicon of the planar gate 503 is also connected to the polysilicon of the second trench gate 502 (ie, the dummy gate). That is to say, there is no gate oxide layer ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


