Automatic Generation Method of Customizable Logic Device Layout and Netlist

Abstract

The invention discloses a method for automatically generating a customizable logic device layout and netlist, including: a layout generation method, including: processing sub-module layout resources, converting the GDS II file format into a CIF format to form a CIF file; Arrange information of chip resources specified by the user, calculate the boundary value, perform the layout operation of the corresponding module, and realize the scale expansion specified by the user; and after realizing the scale expansion specified by the user, write the CIF file of the sub-module to generate a new file in CIF format The layout information of the netlist; and the generation method of the netlist, including: analyzing and processing the netlist describing the module, extracting the information of each port of the top-level module of the netlist, and establishing a database; and according to the port connection rules in the module. The extracted port information is processed to generate a netlist of all rows and columns. The method supports user's personalized customization, is simple to operate, has high speed, can be processed in batches, and has strong scalability.

Description

technical field [0001] The disclosure belongs to the field of hardware design in the field of programmable logic devices, and relates to a method for automatically generating layouts and netlists of customizable logic devices. Background technique [0002] The development of integrated circuit technology and the emergence of Field Programmable Gate Array (FPGA) provide users with the ability to program or reconfigure the system. Users can realize the required logic functions by changing the configuration information without relying on the chip. A specialized chip designed and built by a manufacturer. Since its birth more than 20 years ago, FPGA has gradually evolved from a peripheral device in electronic design to the core of a digital system, and has been widely used in many fields such as the Internet, communications, image processing, automotive electronics, aerospace, and modern military equipment. . [0003] With the increasing scale of FPGA and the increasing complex...

AI Technical Summary

Problems solved by technology

The overall result depends on the front-end circuit design, and does not support user customization. The scalability is relatively poor, and it takes a lot of repetition time, which is not conducive to quickly seizing the market. In addition, FPGA EDA tools need to be redesigned according to each chip version , will also waste a lot of time

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