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A method for preparing high-resistance epitaxial layer with heavily doped silicon substrate for photodetector

A photodetector and epitaxial layer technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as resistivity defect control of P-type silicon epitaxial layers, suppress the influence of impurity self-diffusion, and meet application requirements , the effect of reducing the stress accumulation effect

Active Publication Date: 2020-09-01
CHINA ELECTRONICS TECH GRP NO 46 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to overcome the problems of resistivity and defect control of the P-type silicon epitaxial layer used in the existing photodetectors, by adopting a relatively slow temperature gradient when the temperature of the epitaxial base is raised, and maintaining a constant temperature when it is raised to a certain temperature. A certain period of time to release the stress and inhibit the formation of defects

Method used

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  • A method for preparing high-resistance epitaxial layer with heavily doped silicon substrate for photodetector
  • A method for preparing high-resistance epitaxial layer with heavily doped silicon substrate for photodetector
  • A method for preparing high-resistance epitaxial layer with heavily doped silicon substrate for photodetector

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Effect test

Embodiment 1

[0026] The first step is to load the silicon substrate on the epitaxial base in the epitaxial reaction chamber, and then use nitrogen and hydrogen to purge the doping pipeline and reaction chamber of the epitaxial furnace in sequence. The flow rate of nitrogen is set to 100 L / min, and the flow rate of hydrogen is The flow rate was set at 100 L / min, and the purge time of the doping pipeline and reaction chamber was set at 10 min;

[0027] The second step is to heat the epitaxial susceptor directly from room temperature to 1160°C at a heating rate of 10°C / min, inject hydrogen chloride gas, and polish the surface of the silicon substrate, set the hydrogen chloride flow rate to 3 L / min, and polish The time is set to 1min;

[0028] The third step is to bake the silicon substrate at a constant temperature for 3 minutes to volatilize the impurities on the surface of the silicon substrate and form an impurity depletion region on the surface;

[0029] Step 4: Purging the reaction cham...

Embodiment 2

[0036] The first step is to load the silicon substrate on the epitaxial base in the epitaxial reaction chamber, and then use nitrogen and hydrogen to purge the doping pipeline and reaction chamber of the epitaxial furnace in sequence. The flow rate of nitrogen is set to 100 L / min, and the flow rate of hydrogen is The flow rate was set at 100 L / min, and the purge time of the doping pipeline and reaction chamber was set at 10 min;

[0037] The second step is to heat the epitaxial base from room temperature to 1160°C at a heating rate of 15°C / min, inject hydrogen chloride gas, and polish the surface of the silicon substrate. The flow rate of hydrogen chloride is set to 3 L / min, and the polishing time is set to 1min;

[0038] The third step is to bake the silicon substrate at a constant temperature for 3 minutes to volatilize the impurities on the surface of the silicon substrate and form an impurity depletion region on the surface;

[0039] Step 4: Purging the reaction chamber f...

Embodiment 3

[0047] The first step is to load the silicon substrate on the epitaxial base in the epitaxial reaction chamber, and then use nitrogen and hydrogen to purge the doping pipeline and reaction chamber of the epitaxial furnace in sequence. The flow rate of nitrogen is set to 100 L / min, and the flow rate of hydrogen is The flow rate was set at 100 L / min, and the purge time of the doping pipeline and reaction chamber was set at 10 min;

[0048] The second step is to heat the epitaxial susceptor from room temperature to 1160°C with a heating rate of 15°C / min, and keep the temperature at 900°C, 950°C and 1000°C for 2 minutes, and then introduce hydrogen chloride gas to the surface of the silicon substrate. For polishing, the hydrogen chloride flow rate is set to 3 L / min, and the polishing time is set to 1 min;

[0049] The third step is to bake the silicon substrate at a constant temperature for 3 minutes to volatilize the impurities on the surface of the silicon substrate and form an ...

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Abstract

The invention relates to a method for preparing a high resistivity epitaxial layer for a photoelectric detector by using a heavily-doped silicon substrate. A silicon substrate slice is arranged on anepitaxial base in an epitaxial reaction cavity body, nitrogen and hydrogen are sequentially used to blow an epitaxial furnace doping pipeline and the reaction cavity body. The epitaxial base is heated, and the room temperature is increased to 1160 DEG C. The silicon substrate slice is baked for 3 minutes at the constant temperature, the impurity on the surface of the silicon substrate slice is volatilized, and the surface forms an impurity exhaustion region. The hydrogen is used to blow the reaction cavity, the flow periodically rapidly changes alternatively, and the range of the hydrogen is 40 L / min to 400L / min. A first layer of epitaxial layer is grown. The hydrogen is used to blow the reaction cavity, the flow periodically rapidly changes alternatively, and the range of the hydrogen is40 L / min to 400L / min. A second layer of epitaxial layer is grown. The method has the beneficial effects that: the electrical resistivity of the whole region meets the index of 1000 ohm.cm, and the material meets the use requirements of the photoelectric detector.

Description

technical field [0001] The invention relates to the technical field of semiconductor epitaxial material preparation, in particular to a method for preparing a high-resistance epitaxial layer using a heavily doped silicon substrate for a photodetector. Background technique [0002] At present, silicon-based array photodetectors are developing vigorously in the direction of high precision, fast response, and high signal-to-noise ratio. The requirements for the response wavelength range and detection accuracy of the detector are becoming increasingly stringent. At present, it is generally required that the response non-uniformity is not higher than 10%. , the effective pixel rate reaches 100%, and the failure of one pixel in the array unit will cause the scrapping of the entire chip. The P-type high-resistance epitaxial layer is the key supporting material for the performance of the photoelectric avalanche detector, also known as the π layer. Its resistivity, thickness, and def...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/20H01L31/18
CPCH01L21/20H01L31/18Y02P70/50
Inventor 李明达唐发俊薛兵
Owner CHINA ELECTRONICS TECH GRP NO 46 RES INST