Semiconductor structures and methods of forming them

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate, the substrate including a first region, a second region and a third region, the third region being located between the first region and the second region; forming a dummy gate structure extending from the first region to the second region, the dummy gate structure passing through the third region; forming first source and drain doped regions in the substrate on both sides of the dummy gate structure in the first region respectively ; Forming second source-drain doped regions in the substrate on both sides of the dummy gate structure in the second region; after forming the first source-drain doped region and the second source-drain doped region, forming through the dummy A dielectric opening of the gate structure, the dielectric opening exposes the base of the third region; an interlayer dielectric layer is formed in the dielectric opening, and the top surface of the interlayer dielectric layer is flush with the top surface of the dummy gate structure . The method can reduce the difficulty of forming an interlayer dielectric layer in the dielectric opening.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a method of forming the same. Background technique [0002] With the improvement of the integration of semiconductor devices, the key size of static random access memory (SRAM) is continuously reduced. [0003] The SRAM cell in the prior art usually has a 6T structure. A common SRAM cell with 6T structure usually includes a storage unit and two read-write units. The memory cell includes two pull-up transistors and two pull-down transistors. The two pull-up transistors are connected to the word line, and the two pull-down transistors are connected to the ground line. The memory cell has two storage nodes and two open nodes for storage. 1 or 0 signal; two read-write units are two transfer transistors, one end of each transfer transistor is connected to a storage node and an open node of the memory cell, and the other end is conne...

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Problems solved by technology

[0004] However, the reduced critical size of the SRAM makes the manufacture of the SRAM more difficult

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