Method for fabricating flash memory cell structure
A flash memory cell, floating gate technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, electrical solid-state devices, etc., can solve the problems of increased power consumption, different morphologies, smaller process windows, etc., to reduce resistance and improve performance. , reducing the effect of large changes in erasing current
Active Publication Date: 2018-11-02
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
This will aggravate the current degradation of the erasing unit. On the one hand, a larger gate voltage is required to turn on, which increases power consumption.
Moreover, due to the deviation during etching and the uneven distribution of etching plasma, the amount of silicon loss and the morphology of the bottom active region are different, and these differences will cause differences in the morphology of subsequent ion implantation.
These changes will affect the erasing characteristics of the flash memory cells, and at the same time will cause the process window to become smaller
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[0027] In a preferred embodiment, as figure 1 As shown, a method for preparing a flash memory cell structure is proposed, and the formed structure can be as follows Figure 2-4 Shown, wherein, this preparation method can comprise:
[0028] Step S1, providing a substrate with a P well 10, preparing and forming a first floating gate structure 100 and a second floating gate structure 200 spaced apart from each other on the upper surface of the P well 10, and placing the first floating gate structure 100 and the second floating gate structure The area between the floating gate structures 200 is defined as a central area CE, and the outer area of the first floating gate structure 100 and the second floating gate structure 200 facing away from the central area CE is defined as a peripheral logic area EG;
[0029] Step S2, performing N-type ion implantation on the exposed upper surface of the P well 10 in the central region CE and the peripheral logic region EG, forming a first im...
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The invention relates to the technical field of semiconductors, and in particular, to a method for fabricating a flash memory cell structure, comprising: providing a substrate having P wells, and forming a first floating gate structure and a second floating gate structure on the upper surface of the P wells; performing N-type ion implantation on the exposed upper surfaces of the P wells in the central region and the peripheral logic region; presetting a thickness for the upper surface of the P well exposed in the etched central region; performing N-type ion implantation on the exposed upper surface of the P well in the etched central region to form a source, and lightly doping the exposed upper surface of the P well in the peripheral logic region to form a drain; and the step S5 of formingside walls on the side surfaces of the first floating gate structure and the second floating gate structure adjacent to the peripheral logic region, so that the formed source may be effectively connected to the channel, and the resistance of the source terminal is reduced, thereby reducing the problem of a large change in the erased current caused by unstable loss of the source active region, andimproving the performance related to erasure.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a flash memory unit structure. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly manufactured at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the growing maturity of new technology nodes also urges flash memory cells to be produced with high-node technologies. It means that the size of the flash memory unit needs to be reduced, and the reduced width of the active area of the flash memory unit and the length of the channel will affect the performance of the flash memory unit. [0003] In order to i...
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Login to View More IPC IPC(8): H01L27/11521H01L27/11531H01L21/336
CPCH01L29/66825H10B41/42H10B41/30
Inventor 田志彭翔
Owner SHANGHAI HUALI MICROELECTRONICS CORP