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Clock edge-triggered method for phase-splitting of phase-locked loops in series
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A clock edge and phase-locked loop technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of low performance, high system operating frequency, low resolution, etc., to achieve lower operating frequency, performance measurement effect, high resolution rate effect
Active Publication Date: 2022-03-15
HARBIN INST OF TECH
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[0015] The purpose of the present invention is to solve the problems of low resolution, high systemoperating frequency and low performance of the existing clock phasing method, and provide a clock phasing method triggered by the clock edge of the serial phase-locked loop
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specific Embodiment approach 1
[0034]Specific implementation mode one: the clock phase splitting method triggered by the clock edge of the serial phase-locked loop described in this implementation mode, the specific process is:
[0035] Step 1, input clock signal 100MHz to the input terminal of a phase-locked loop;
[0036] Step 2. Multiply the clock signal from 100MHz to 200MHz, shift the phase of the high-level segment of the input clock eight times, and set the phase shift angles CLK[0]~CLK[7] to 0°, 22.5°, and 45° respectively , 66.5°, 90°, 112.5°, 135°, 157.5°;
[0037] Step 3, input the clock signal 100MHz to the input end of another phase-locked loop;
[0038] Step 4. Multiply the clock signal from 100MHz to 200MHz, shift the phase of the high-level segment of the input clock eight times, and set the phase shift angles CLK[8]~CLK[15] to 11.25°, 33.75°, and 56.25° respectively , 78.75°, 101.25°, 123.75°, 146.25°, 168.75°;
[0039] Step 5, using the edges of the sixteen clock signals after the frequ...
specific Embodiment approach 2
[0048] Embodiment 2: This embodiment further describes Embodiment 1. The edges of the sixteen clock signals in step 5 include rising edges and falling edges of the sixteen clock signals.
specific Embodiment approach 3
[0049] Specific implementation mode three: this implementation mode further explains implementation mode one, and the method for extracting the positions of 0→1 transition and 1→0 transition in Count[0]~Count[29] described in step 7 is:
[0050] Calculate Count[n] and Count[n+1]:
[0051] When event_up[n]=(~Count[n])&Count[n+1]] occurs, it is the position where 0→1 jumps;
[0052] When event_down[n]=(~Count[n+1])&Count[n] occurs, it is the position of 1→0 transition;
[0053] Among them, n=0,1,...,29.
[0054] The present invention proposes a precision time interval measurement method based on FPGA, which divides the time interval measurement into two parts: "coarse" measurement and "fine" measurement. It relies on the clock phase division method to perform time interpolation, so as to obtain higher time resolution.
[0055] The most basic method in the traditional time interval measurement technology is the pulse counting method. The pulse in the pulse counting method ref...
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Abstract
The clock phase-splitting method triggered by the clock edge of the series phase-locked loop belongs to the field of time interval measurement, and aims to solve the problems of low resolution, high systemoperating frequency and low performance of the existing clock phase-splitting method. The specific process is: input the clock signal 100MHz to the input terminal of a phase-locked loop; multiply the frequency to 200MHz, and shift the phase of the high-level segment eight times; input the clock signal to another input terminal of the phase-locked loop; multiply the frequency to 200MHz , shift the phase of the high-level segment eight times; use the edge of the phase-shifted frequency multiplier of the series phase-locked loop as the trigger signal; perform clock synchronization on the signal under test; Timing constraints; extract the position where the measured signal level jumps at the trigger time; when the rising edge detection function of the measured signal or the falling edge detection function of the measured signal detects a rising edge, output a high level, otherwise output Low level; complete clock phase split. Used for time interval measurements.
Description
technical field [0001] The invention relates to a time interval measurement method, which belongs to the field of time interval measurement. Background technique [0002] Time is one of the fundamental units of physics. We usually refer to time in two senses: one meaning refers to moments, and the other refers to time intervals. Moment refers to a certain instant of time that passes continuously, and it refers to when an event occurs; while time interval refers to how long the interval between two instants is, and it refers to the duration of an event. [0003] Precise time, as a basic physical parameter in scientific research, scientific experiments and engineering technology, provides an essential time-base coordinate for the measurement and quantitative research of all dynamical systems and time series processes. Precise time not only plays an important role in basic research fields such as nuclear physics research, particle physics research, geodynamics research, relat...
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