Semiconductor structure and formation method thereof

[0032] The wafer test structure of the present invention will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the beneficial effects of the present invention . Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0033] There are many problems in the formation method of the semiconductor structure, and it is difficult to guarantee the stable performance of the formed semiconductor structure.

[0034] After research, it is found that as the size of the fin used to form the fin field effect transistor continues to shrink, the bottom of the source region and the drain region formed in the fin is prone to bottom punch through (punch through), that is, the source region and the drain region. A short circuit occurs between the bottoms, generating a leakage current at the bottoms of the source and drain regions. In order to overcome the bottom punch-through phenomenon, one method is to implant anti-type ions in the region between the bottom of the source region and the drain region to isolate the bottom of the source region and the drain region.

[0035] Figure 1 to Figure 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0036] Please refer to figure 1 , a substrate is provided, and a fin portion 101 and a hard mask 110 on top of the fin portion 101 are disposed on the substrate 100 . The substrate includes: a first transistor region A and a second transistor region B.

[0037] continue to refer figure 1 , forming an anti-penetration layer 102 on the substrate 100 , the surface of the anti-penetration layer 102 is lower than the top surface of the fin portion 101 .

[0038] Please refer to figure 2 , performing ion implantation on the anti-puncture layer 102, the implanted anti-puncture ions.

[0039] Please refer to image 3 , after the anti-puncture ions are implanted, an annealing treatment is performed to diffuse the anti-puncture ions into the bottom of the fin portion 101 .

[0040] Wherein, during the annealing process, the anti-puncture ions are easy to diffuse to the top of the fin portion 101 , thus causing the threshold voltage of the subsequently formed transistor to increase, thereby affecting the performance of the transistor.

[0041] In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which fins are arranged, and there are fin gaps between adjacent fins; A hard mask is arranged above the hard mask; an anti-penetration layer is formed above the hard mask, and there are anti-penetration ions in the anti-penetration layer; an anti-diffusion layer is formed, and the height of the anti-diffusion layer is lower than the height of the fins , implanting anti-diffusion ions into the gap of the fin, the anti-diffusion ions can prevent the diffusion of the anti-puncture ions to the top of the fin; removing the hard mask; performing annealing.

[0042] Wherein, in the forming method of the semiconductor structure of the present invention, before performing the annealing treatment, an anti-diffusion layer is formed, and anti-diffusion ions are implanted into the gap between adjacent fins, that is, the anti-diffusion layer and the anti-penetration layer. The ions are located on the top of the anti-diffusion layer and the anti-penetration layer. At the same time, due to the doping characteristics, the doping concentration gradually decreases from the doping source of the anti-diffusion ions outward, so the anti-diffusion ions also exist in the fins, and the anti-diffusion ions The ions in the anti-penetration layer can be prevented from diffusing to the top of the fin, so that the anti-penetration ions diffusing into the channel of the transistor can be reduced. Therefore, the method for forming the semiconductor structure can reduce the impact of the anti-puncture ions on the threshold voltage of the formed transistor, thereby improving the performance of the formed semiconductor structure. In addition, since the anti-diffusion ions are formed in the anti-diffusion layer, the process operation is more convenient, and at the same time, the ions in the anti-penetration layer are effectively prevented from diffusing to the top of the fin.

[0043] In addition, the anti-puncture layer of the present invention has anti-puncture ions, which can prevent or reduce the breakthrough of the source region and the drain region in the semiconductor structure, thereby reducing the leakage current.

[0044] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0045] Figure 4 to Figure 13 It is a structural schematic diagram of each step of an embodiment of the method for forming a semiconductor structure of the present invention.

[0046] In this embodiment, the substrate includes: a first transistor region A and a second transistor region B. In other embodiments, the substrate may also only include the first transistor region or the second transistor region.

[0047] In this embodiment, the first transistor region A is used to form an NMOS transistor; the second transistor region B is used to form a PMOS. In other embodiments, the first transistor region can also be used to form a PMOS transistor; the second transistor region is used to form an NMOS.

[0048] Please refer to Figure 4 , the substrate further includes: a hard mask 204 located on the top of the fin 202, the hard mask 204 can protect the top of the fin 202 from implanting anti-puncture ions during the subsequent anti-puncture ion implantation process, thereby reducing Effect of anti-puncture ion implantation on transistor performance.

[0049] In one embodiment of the present invention, the step of forming the substrate includes: providing an initial substrate; forming a patterned hard mask 204 on the initial substrate; using the hard mask 204 as a mask, patterning The initial substrate forms a substrate 200 and a fin 202 on the substrate 200, and the fin 202 is used to form a transistor channel.

[0050] Optionally, after the hard mask is set, an oxide layer 203 is covered on the hard mask 204 , and the oxide layer 203 covers the hard mask 204 , the fins 202 and the fin gaps 20 . The material of the oxide layer 203 can be SiO 2. The oxide layer 203 is subsequently removed before the formation of the anti-puncture layer.

[0051] Please refer to Figure 5 , remove the oxide layer 203, and form an anti-penetration layer 205, the anti-penetration layer 205 has anti-penetration ions, the anti-penetration layer covers the fins and fin gaps, and is used to prevent the source region and the fin gap in the semiconductor structure. The drain region is punched through, thereby reducing the leakage current.

[0052] Please refer to Image 6 , in one embodiment of the present invention, the substrate includes a first transistor region A and a second transistor region B. Optionally, the first transistor region A is an NMOS transistor, and the second transistor region B is a PMOS transistor. The doping type of the anti-punching ion is opposite to the doping type of the transistor in the corresponding region. Optionally, the punch-through preventing ions in the first transistor region are P-type ions, such as boron ions or boron fluoride ions, and the punch-through preventing ions in the second transistor region are N-type ions, such as phosphorus ions or arsenic ions.

[0053] Optionally, the anti-puncture layer is only provided in the region A of the first transistor region. Specifically, in Figure 5 Based on the above process, the part of the anti-puncture layer in the second transistor region B is etched away, and only the part of the anti-puncture layer in the first transistor region A remains. Alternatively, in the process step of depositing the punch-through prevention layer, a mask is used to block the second transistor region B, so that the punch-through prevention layer is only formed on the part of the punch-through prevention layer in the first transistor region A. This setting is because compared with PMOS transistors, NMOS transistors have more severe loss of dopant ions (eg, B ions), and thus are more likely to suffer from current breakthrough.

[0054] Optionally, in an embodiment of the present invention, the substrate includes a first transistor region A and a second transistor region B. The first anti-punching ion implantation is performed on the first transistor region A, and the second anti-punching ion implantation is performed on the second transistor region B. In other embodiments, when the substrate only includes the first transistor region or the second transistor region, the step of anti-puncture ion implantation only includes: performing the first anti-puncture ion implantation on the first transistor region, or The second transistor region is subjected to second anti-puncture ion implantation.

[0055] If the thickness of the anti-penetration layer 205 is too large, material waste is likely to occur; if the thickness of the anti-penetration layer 205 is too small, it is difficult to fully prevent the source-drain breakthrough of the formed transistor. Therefore, in this embodiment, the thickness of the through layer 205 is 20 angstroms to 60 angstroms.

[0056] In this embodiment, if the concentration of the punch-through ions in the punch-through prevention layer 205 is too high, the punch-through prevention ions will easily diffuse through the diffusion prevention layer to the top of the fin 202, thereby easily affecting the performance of the formed transistor; if the punch-through prevention The concentration of the anti-puncture ions in the layer 205 is too low, and it is difficult to prevent source-drain breakthrough of the formed transistor. Therefore, in this embodiment, the concentration of anti-puncture ions in the anti-puncture layer 205 is 1.0E13 atoms/cm 2 -1.0E15 atoms/cm 2.

[0057] In this embodiment, the process parameters of anti-puncture ion implantation include: the implantation dose is 1.0E13 atoms/cm 2 -1.0E15 atoms/cm 2; The injection energy is 5KeV-100KeV.

[0058] Please refer to Figure 7 , in one embodiment of the present invention, a protective layer 206 is formed above the anti-puncture layer 205, and the protective layer 205 prevents the anti-puncture ions in the anti-puncture layer 205 from diffusing upward during annealing. Since the purpose of the anti-puncture layer 205 is to prevent the source region and the drain region in the semiconductor device from being penetrated, this purpose cannot be achieved if the anti-puncture ions diffuse upwards. Therefore, the protective layer 205 is provided to prevent the upward diffusion of the anti-puncture ions. Optionally, the protective layer is made of one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN.

[0059] Please refer to Figure 8 , in one embodiment of the present invention, an initial anti-diffusion layer 208 is formed, and the initial anti-diffusion layer 208 covers the entire fin portion 202, that is, covers the top and side surfaces of the fin portion, and the material of the initial anti-diffusion layer 208 can be two Silicon oxide, the initial anti-diffusion layer 208 can be formed by a fluid chemical vapor deposition (FCVD) process. Compared with other deposition processes, the fluid chemical vapor deposition material uses a polymer material as a carrier, and has good fluidity and filling capacity.

[0060] Subsequently, a first annealing process is performed on the initial anti-diffusion layer 208. The temperature of the first annealing process is 400°C-650°C. The first annealing process is mainly to volatilize the polymer material. In the first annealing process, Si-O bonds are gradually formed. Subsequently, thermal ion implantation is performed on the initial anti-diffusion layer 208, and the temperature of the thermal ion implantation process is 450°C-500°C. Since the material also contains a large amount of water, there are hydrogen bonds between water molecules. The purpose of this thermal ion implantation is to use the stress of the implanted ions to break the redundant hydrogen bonds. Optionally, the ion implanted in the thermal ion implantation process is He, the implanted energy is 1-50Kev, and the implanted dose is 1.0e14-1.0e19atm/cm 2. Optionally, a second annealing process may be performed on the initial anti-diffusion layer 208, the temperature of the second annealing process is 500° C.-700° C. to remove H ions therein, and simultaneously cure the formed initial anti-diffusion layer;

[0061] Finally etch the initial anti-diffusion layer 208 to make its height lower than that of the fins to form the anti-diffusion layer 207 (such as Figure 9 shown). In this embodiment, a three-step process is used to prepare the anti-diffusion layer, combined with annealing, thermal ion implantation and other processes, and the introduction of the thermal ion implantation process reduces the densification temperature of the FCVD oxide, so that the quality of the formed diffusion layer is higher.

[0062] In this embodiment, the materials of the initial diffusion prevention layer 208 and the diffusion prevention layer 207 may be silicon oxide or silicon oxynitride.

[0063] Please refer to Figure 10 After the anti-diffusion layer 207 is formed, the anti-penetration layer 205 and the protection layer 206 are etched so that the heights of the anti-penetration layer 205 and the protection layer 206 are flush with the anti-diffusion layer.

[0064] Please refer to Figure 11 , implant anti-diffusion ions into the fin gap 20, and the anti-diffusion ions can prevent the ions in the anti-penetration layer from diffusing to the top of the fin. Specifically, the anti-diffusion ions are implanted in the anti-diffusion layer 207, the protective layer 206 and the anti-penetration layer 205, due to the doping characteristics, the doping concentration gradually decreases from the doping source of the anti-diffusion ions to the outside, so the anti-diffusion ions also exist in the fins at the same time, for example, the anti-diffusion ions exist in the Figure 12 In the doped region 209 shown, the anti-diffusion ions can prevent the ions in the anti-puncture layer from diffusing to the top of the fin, thereby reducing the anti-puncture ions that diffuse into the channel of the transistor.

[0065] The element of the anti-diffusion ion is an element of the fourth main group or an atomic element that is not easily bonded to the fin atoms. The number of electrons in the outermost layer of the atoms of the fourth main group element is the same as that of the fin portion 202, so it is not easy to form many electrons in the fin portion 202, and therefore, it is not easy to change the conductivity of the fin portion 202. ; Atoms that are not easy to bond with fin atoms are not easily activated during the subsequent annealing process. Therefore, atoms that do not easily bond to fin atoms are also less likely to change the conductivity of the fin 202 . In addition, the anti-diffusion ions can enter the gaps formed by the atoms of the fins 202 , thereby preventing the anti-puncture ions from diffusing to the top of the fins 202 through the gaps, thereby improving the performance of the formed semiconductor structure.

[0066] Therefore, the anti-diffusion layer 207 can prevent the anti-puncture ions in the fin 202 from diffusing to the top of the fin 202 during the subsequent annealing process, thereby reducing the anti-puncture ions that diffuse into the channel of the transistor and reducing the anti-puncture ion pair. The effect of the threshold voltage of the formed transistor, thereby improving the performance of the formed semiconductor structure.

[0067] In this embodiment, the anti-diffusion ions include: one or more combinations of carbon ions, germanium ions and nitrogen ions. After the carbon ions, germanium ions and nitrogen ions enter the atomic gap of the fin 202 , they can prevent the anti-puncture ions from diffusing to the top of the fin 202 . In addition, nitrogen ions are not easy to be activated during the annealing process so as not to affect the conductivity of the fin portion 202 ; carbon and germanium are elements of the fourth main group, and are not easily activated during the annealing process to affect the conductivity of the fin portion 202 .

[0068] If the concentration of anti-diffusion ions in the anti-diffusion layer 207 is too high, it will easily affect the conductivity of the fin 202 and reduce the transistor performance; 202 top spread. Therefore, in this embodiment, the concentration of the anti-diffusion ions in the anti-diffusion layer 207 is 1.0E13 atoms/cm 2 -1.0E16 atoms/cm 2.

[0069] In this embodiment, the process parameters of anti-diffusion ion implantation include: the implantation energy is 1KeV-30KeV; the implantation dose is 1.0E13atoms/cm 2 -1.0E16 atoms/cm 2.

[0070] Please refer to Figure 13 , and finally remove the hard mask and anneal the semiconductor structure.

[0071] The annealing treatment is used to activate the anti-punching ions, so that the anti-punching ions can prevent source-drain punch-through. During the annealing process, the anti-diffusion ions in the anti-diffusion layer 207 can block the diffusion of the anti-puncture ions in the anti-puncture layer to the top of the fin 202, thereby reducing the impact of the anti-puncture ions on the formed transistor. influence, thereby improving the performance of semiconductor structures.

[0072] In this embodiment, the annealing temperature of the annealing treatment is greater than or equal to 850°C.

[0073] It should be noted that, in this embodiment, after performing the degradation treatment, the forming method further includes: forming a gate structure across the fin 202 , the gate structure covers a part of the sidewall of the fin 203 and top surface.

[0074] In this embodiment, the top of the anti-penetration layer is flush with the bottom of the anti-diffusion layer. In other embodiments, the top of the anti-penetration layer can also be lower than the bottom of the anti-diffusion layer, or the top of the anti-penetration layer is higher than the top of the anti-diffusion layer, and the bottom of the anti-penetration layer below the top of the diffusion barrier.

[0075] Figure 14 It is a schematic diagram of the formation steps of the semiconductor structure of the present invention.

[0076] The present invention also includes a semiconductor structure made by the above-mentioned semiconductor forming method.

[0077] To sum up, in the semiconductor forming method of the present invention, an anti-penetration layer is formed, which can prevent or reduce the penetration between the source region and the drain region, thereby reducing the leakage current;

[0078] Further, an anti-diffusion layer and a protective layer are arranged next to the anti-puncture layer, the protective layer can prevent the anti-puncture ions from diffusing to the outside, and the anti-diffusion layer can reduce the anti-puncture ions that diffuse into the channel of the transistor.

[0079] Further, the anti-diffusion ions are formed in the anti-diffusion layer in the gap between adjacent fins, making the process more convenient, and effectively preventing the ions in the anti-penetration layer from diffusing to the top of the fin.

[0080] Further, the example of the present invention adopts a three-step process to prepare the anti-diffusion layer, combined with annealing, thermal ion implantation and other processes, the introduction of thermal ion implantation process reduces the temperature of FCVD oxide densification, so that the quality of the formed diffusion layer is higher.

[0081] Therefore, the method of forming a semiconductor structure can improve the performance of the formed semiconductor structure.

[0082] Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.