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Novel message controller and communication method thereof, which can realize multiprocessor communication at high speed

A multi-processor and controller technology, applied in the field of processors, can solve problems such as too strict restrictions on multi-core system-on-chip architecture, hardware resources occupied by multi-core communication, and lack of versatility of modules, etc., to achieve fast writing and reading speeds , Reduce the difficulty of the program and improve the response speed

Active Publication Date: 2018-12-21
苏州硅岛信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this structure is that it takes up a lot of hardware resources to realize inter-multi-core communication, and requires a dedicated processor as the core scheduling processor, which cannot be used for other purposes; The on-chip network or bus corresponding to the technology to be used
[0006] (4) Some manufacturers have designed hardware-based multi-core communication modules, but these modules are not universal and are only used between the manufacturer's specific processor cores

Method used

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  • Novel message controller and communication method thereof, which can realize multiprocessor communication at high speed
  • Novel message controller and communication method thereof, which can realize multiprocessor communication at high speed

Examples

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Embodiment 1

[0034] Such as figure 1 Shown is a new type of message controller that can realize multi-processor communication at high speed. The above figure is an example to illustrate that message controllers 0 and 1 store the control registers of the queue. Each register obtains the queue status by reading and writing the control register. The data body of the message is stored in a memory (memory A in the figure above). The memory for storing messages can be outside the message controller, in a certain memory in the system, or inside the message controller. The processor obtains the memory address where the message is stored by reading the control register.

[0035] Processor 1 will continuously write the message data into memory A and update the control register in message controller 1, and processor 0 will continuously obtain the message storage location from message controller 1 and read memory A to obtain message data, realizing from Message and data transfer from Processor 1 to...

Embodiment 2

[0039] Such as figure 2 A novel message controller that can realize multi-processor communication at a high speed as shown includes 3 groups of message controller register files, and the message controller register files are connected to processors through a bus adapter, and the message controller register files are composed of Write pointer register, read pointer register, effective unit number register, effective unit number register, memory base address register, and memory capacity register.

[0040] The minimum unit bit width in the register file of the message controller may be a byte (8 bits), a halfword (16 bits), or a word (32 bits).

[0041] The message transmission between the message controller register files is one-way transmission or two-way transmission.

[0042]The write pointer register (WPTR): record the current write address of the message writer in the memory, this address is the address of the next unit to be written, and the write pointer register will ...

Embodiment 3

[0052] A novel message controller communication method capable of realizing communication between multiprocessors at high speed, comprising the following steps:

[0053] a. The message controller register obtains the queue status by reading and writing the control register;

[0054] b. Store the data body of the message in the memory;

[0055] c. The processor obtains the memory address where the message is stored by reading the control register;

[0056] Among them, the writer needs to calculate "WVALID=QSIZE-VALIDNUM" when writing, and WVALID is the maximum number of queue units that can be written. Determine whether the value of WVALID is greater than or equal to the amount of data to be written this time, if it is greater than or equal to the amount of data to be written, it can be written and WPTR is updated, otherwise it cannot be written and continues to wait;

[0057] The reader can complete the message reading operation by setting the interrupt reporting register an...

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Abstract

The invention relates to a novel message controller and a communication method thereof, which can realize high-speed communication between multiple processors, includes one or more sets of message controller register files, the message controller register file is connected to the processor through a bus or a network, The message controller register file is connected with a memory through a bus ora network. The message controller register file is composed of a write pointer register, a read pointer register, an effective unit number register, an effective unit number register, a memory base address register and a memory capacity register. The message controller register file comprises a write pointer register, a read pointer register, a valid unit number register, a memory base address register and a memory capacity register. The advantages of this scheme are: high speed communication; There are no restrictions on the types of queues, including, but not limited to, first-in, first-outqueues and first-in, second-out queues; The types of queues can be selected according to the application scenario. Each processor can read and write to this message controller via an on-chip bus or network, and the message controller itself does not specify directionality.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a novel message controller capable of realizing communication among multi-processors at high speed. Background technique [0002] With the popularization of multi-core processor systems, communication between multi-cores has become a major problem that affects the cooperative work among multi-cores. The current multi-core communication methods are: [0003] (1) The application program working on different processors, as the process or thread of the operating system, the communication between each process or thread is handed over to the operating system running on the processor core through the information transfer and data exchange between thread processes. of. The problem with this method is that for those specific multi-core systems without an operating system or some special domains, it is not suitable to realize multi-core communication. [0004] (2) Use software to imp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167G06F15/80
CPCG06F15/167G06F15/8076
Inventor 葛松芬
Owner 苏州硅岛信息科技有限公司
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