Dot matrix display device and time display device

A display device and dot matrix technology, applied to static indicators, nonlinear optics, instruments, etc., to achieve the effects of shortened forwarding time, simplified wiring structure, and low power consumption

Active Publication Date: 2018-12-21
CASIO COMPUTER CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, although a backlight is provided in the case of a transmissive LCD, a backlight is not provided in the case of a reflective LCD.

Method used

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  • Dot matrix display device and time display device
  • Dot matrix display device and time display device
  • Dot matrix display device and time display device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0056] refer to Figure 1 ~ Figure 13B The dot matrix display device 11 according to this embodiment will be described. figure 1 It is a block circuit diagram showing the overall configuration of the dot-matrix display device 11 . exist figure 1 A configuration example of a dot-matrix display device 11 including a display unit 10 for black-and-white display with a pixel count of 65536 dots (256 dots in length×256 dots in width) is shown in FIG.

[0057] The dot-matrix display device 11 according to this embodiment is, for example, figure 1 As shown, it includes: a signal supply unit 6; a pixel rewriting control unit 5; a display unit 10 having pixel electrode units 4 arranged in a matrix including holding circuits (memory); direction of crossing (e.g. figure 1 The gate decoder circuit 12 of the gate signal of the gate signal line 1 (GL1 ~ GL256) arranged on the top-to-bottom direction of the top-to-bottom direction); generates a selection (set to an enabled state) in o...

no. 2 Embodiment approach

[0094] In the above-mentioned first embodiment, the general overall operation of the dot matrix display device according to the present invention was described, but in this embodiment, the drive control in the pixel rewriting control unit 5 performed in units of one pixel will be described. Case.

[0095] Figure 12A as well as Figure 12B It is a timing chart for explaining the operation of the pixel rewriting control unit 5 of the dot matrix display device 11 according to the present embodiment. which is, Figure 12A as well as Figure 12B It is a timing diagram of random access for rewriting drivers by randomly accessing addresses one by one. First, in the first cycle and the second cycle during which the data identification signal DEN is inactive, the serial signal SI[7:0] including the gate address signal and the source address signal is input from the signal supply unit 6 to the pixel rewriting control Part 5 of the shift register circuit 22. Thereafter, the data i...

no. 3 Embodiment approach

[0097] In the above-mentioned second embodiment, the case where the drive control is performed in units of one pixel is described, but in this embodiment, the case where the pixel rewriting control unit 5 is to be controlled is partially continuous is described.

[0098] Figure 13A as well as Figure 13B It is a timing chart for explaining the operation of the pixel rewriting control unit 5 of the dot matrix display device according to the present embodiment. which is, Figure 13A And 13B is a timing chart in the case of accessing consecutive addresses and performing rewriting drive. From the 1st cycle to the 3rd cycle is the same as above 12A and Figure 12B The operation is the same for the random access shown above. The gate address (GS(A)), source address (SS(B)), and image signal (DATA(A, B)) serially input in the third cycle are taken into the internal register, and rewriting is executed by The enable signal ENB of is activated, and the image data (DATA (A, B)) is ...

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Abstract

Provided is a dot matrix display device capable of implementing a combination of still picture display and motion picture display with extremely low power consumption, in which the wiring structure issimplified by reducing the number of terminals for inputting signals and the signal transfer time is shortened. This dot matrix display device 11 includes a pixel rewriting control unit 5 and decoderunits 12, 13, 14. On the basis of a serial signal including an address signal for specifying the address of a pixel electrode unit 4 and an image signal to be supplied to the pixel electrode unit 4,the pixel rewriting control unit 5 generates, corresponding to the pixel electrode unit 4, a gate selection signal for specifying an address in one direction, a source selection signal for specifyingan address in another direction intersecting with the one direction, and image data. The decoder units 12, 13, 14 supply a gate signal to activate the gate signal line corresponding to the pixel electrode unit 4 on the basis of the gate selection signal, generate a source signal to activate the source signal line corresponding to the pixel electrode unit 4 on the basis of the source selection signal, and supply the image data to the pixel electrode unit 4 corresponding to the activated source signal line.

Description

technical field [0001] The present invention relates to a dot matrix type display device and a time display device in which a large number of pixel electrode portions including thin film transistor (Thin Film Transistor: TFT) elements are formed on a substrate. Background technique [0002] Various dot matrix type display devices have been manufactured in the past. For example, a TFT array-side substrate on which a large number of pixel electrodes including TFT elements are formed, and a color filter-side substrate on which a color filter and a black matrix are formed are opposed to each other, and these substrates are bonded at a predetermined interval. A liquid crystal display device (Liquid Crystal Display: LCD) is produced by filling and encapsulating liquid crystal between the substrates. [0003] The configuration of a conventional dot-matrix display device will be described (see, for example, Patent Document 1). Figure 14 It is a block circuit diagram showing the ba...

Claims

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Application Information

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IPC IPC(8): G09G3/36G02F1/133G09G3/20
CPCG02F1/133G09G3/20G09G3/36G09G3/3648G09G2310/08G09G3/3688G09G2330/021G09G2300/0857G09G2300/0426G09G2310/0205G09G2340/0492G09G2310/04
Inventor 粕尾智夫山川英司铃木隆信
Owner CASIO COMPUTER CO LTD
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