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A semiconductor device and a manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of reducing the transconductance of MOS devices, affecting the performance of MOS devices, etc., and achieve the advantages of reduced thickness, high integration, and low process cost Effect

Inactive Publication Date: 2019-01-11
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, with the continuous reduction of device feature size, higher requirements are placed on the performance of MOS devices. Too thick gates will directly affect the depletion of gate electrodes, reduce the transconductance of MOS devices, and affect the performance of MOS devices. performance

Method used

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  • A semiconductor device and a manufacturing method thereof
  • A semiconductor device and a manufacturing method thereof
  • A semiconductor device and a manufacturing method thereof

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Embodiment Construction

[0040] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0041] In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

[0042] Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the gener...

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Abstract

The invention provides a manufacturing method of a semiconductor device. A first gate layer and a second gate layer are formed in the flash memory region and the MOS region at the same time, respectively, a protective layer is also formed on the first gate layer, the protective layer prevents the floating gate layer of the storage area from being damaged in the sidewall process and the previous process, to protect the floating gate, as oppose to a method of protecting a floating gate layer by increasing the thickness of a gate layer over a floating gate layer of a flash memory region. The increase in the thickness of the second gate layer of the MOS region formed together with the first gate layer of the flash memory region is avoided, so that the thickness of the second gate layer of theMOS device can be effectively reduced while the memory performance of the flash memory of the flash memory region is satisfied, the transconductance of the MOS device can be improved, and the performance of the device can be further improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, memory has been widely used. Floating gate flash memory is a kind of non-volatile memory, which has the advantages of high integration, fast storage speed and easy erasing and rewriting. [0003] In a specific application, a floating gate flash memory device is usually integrated with a peripheral circuit composed of a MOS (Metal-Oxide-Semiconductor, metal oxide semiconductor) device, and the control gate of the floating gate flash memory device is connected to the MOS device of the peripheral circuit. The gate is formed together, and in order to ensure the storage performance of the floating gate flash memory, the thickness of the control gate must be ensured, which will make the gate of the MOS device too thick. Howeve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11517H01L27/11521H10B41/00H10B41/30
CPCH10B41/00H10B41/30
Inventor 罗清威李赟周俊
Owner WUHAN XINXIN SEMICON MFG CO LTD
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