Thin 3D fan-out packaging structure and wafer-level packaging method

Abstract

The invention discloses a thin 3D fan-out packaging structure and a wafer-level packaging method. Grooves and blind holes whose depths are smaller than those of the grooves are made in a carrier plate; a lining is deposited on the inner wall of the blind hole; a dielectric layer is deposited on at least the bottom of the groove; the blind hole is filled with a metal material; a chip is buried in the groove; a chip welding pad or the blind hole metal material is connected through metal rewiring; the second surface of the carrier plate is thinned, and the metal material in the blind hole is exposed; an electrical derivation point is made on the metal rewiring or the metal material, a stacking chip or a printed circuit board is electrically connected with the chip welding pad through the electrical derivation points on the first surface and the second surface of the carrier plate, and 3D fan-out packaging is realized. The TSV and the lining are firstly made, the TSV and lining depositionquality problem can be solved, and ultra-high density interconnection is better realized; and the dielectric layer is deposited on the bottom part of the groove, the chip can be protected from being etched, and after the carrier plate is thinned, the height difference between the dielectric layer and the TSV hole can accommodate part of second electrical derivation points, and the stacking thickness is reduced.

Description

technical field [0001] The invention relates to the technical field of 3D fan-out wafer-level packaging, in particular to a thin 3D fan-out packaging structure and a wafer-level packaging method. Background technique [0002] 3D fan-out wafer-level packaging is to realize fan-out packaging of chips at the wafer size level. It is also an advanced packaging process with a large number of I / Os and good integration flexibility. It can realize multiple chips in vertical and horizontal directions in a package. integrated. As such, fan-out wafer-level packaging is currently being developed into next-generation packaging technologies such as multi-die, low-profile packaging, and 3D SiP. With the development of electronic products in the direction of thinner, lighter, higher pin density, and lower cost, the emergence of 3D fan-out wafer-level packaging technology provides an opportunity for the packaging industry to develop multi-functional small-size packaging. [0003] In existin...

AI Technical Summary

Problems solved by technology

Since there are many kinds of material structures on the silicon substrate before making TSVs, the temperature in the process is greatly limited, so the production of TSV lining (usually silicon oxide higher than 200°C PECVD) is greatly restricted. It is difficult to guarantee the quality of lining preparation. In addition, TSV etching also has process problems such as bottom over-etching, which makes it difficult to improve yield.

Planar stacking, the height of stacked packages cannot be further reduced

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