A semiconductor memory aging test core board

Abstract

The invention belongs to the technical field of semiconductor memory aging testing, and discloses a core board for semiconductor memory aging testing, which generates test vectors in real time according to the parameter configuration of a host computer, outputs various types of test signals and various test patterns, and performs test signals on the test signals. Delay adjustment, enhanced driving, processing of waveform control, and compensation of power signal to generate more accurate power signal of test signal; improved user's ability to customize test waveform and flexibility; test core board has partitioned memory , save the real-time comparison test data in partitions during the test process, and control and fail to analyze the failed DUT test process through the data stored in the partitions, realizing the control and failure analysis of a single DUT test process in the burn-in test; provided by memory such as DRAM The storage space of each DUT saves enough test information for each IO of each DUT, so that DUT manufacturers can conduct statistical analysis on each batch of failed DUTs, improve the yield rate, and enhance product reliability.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory burn-in test, and more specifically relates to a semiconductor memory burn-in test core board. Background technique [0002] Semiconductor memory has a certain failure probability, and the relationship between the failure probability and the number of times of use conforms to the characteristics of the bathtub curve. The failure probability of the memory is high at the beginning of use, and the failure probability is greatly reduced after a certain number of times of use, until it is close to or reaches its use. After the lifetime, the failure probability of the memory will increase again. So far, no memory manufacturer has dared to ignore the failure problem of semiconductor memory. Generally, the aging test (Test During burn-in, TDBI) is used to accelerate the occurrence of memory failure probability, and directly let it enter the product stable period to solve this problem. [000...

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Problems solved by technology

[0010] The Chinese patent with the publication number CN102467973A discloses a memory testing method and device, which mentions that when the memory is aging, the heat generated by its own power consumption is used to control the aging temperature, so as to solve the problem of uneven temperature distribution and temperature error caused by external heating. It is mentioned that the controller and signal generator are used to test the memory, and the row-column matrix control method is mainly used; however, it does not involve the recording and management analysis of the test process, and this method is not suitable for low-temperature aging tests and has certain limitations

[0011] The Chinese patent with the publication number CN107271879A discloses a semiconductor chip aging test device and method, which is a method for reducing the transmission distortion of the test clock signal, mainly by moving the high-frequency crystal oscillator that generates the clock signal to the vicinity of the chip socket under test. And multiple clock sources can be selected through the multiplexer, so that the chip can be tested for durability aging at room temperature; there is no mention of high and low temperature aging test solutions, and there is no management analysis of the test process and results

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