An interleaved matching filtering method suitable for specific integrated circuit design

A matched filter and integrated circuit technology, applied in CAD circuit design, calculation, electrical and digital data processing, etc., can solve the problem of large consumption of logic resources, and achieve the effect of reducing design complexity, simplifying design structure, and saving logic resources.

Active Publication Date: 2019-02-26
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Application Information

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Problems solved by technology

[0004] In order to solve the problem of excessive consumption of logical resources when performing matched filtering on signals sampled at N times the chip rate of spread spectrum signals, the present invention discloses an interleaved matched filtering method suitable for application-specific integrated circuit design. Afterwa

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  • An interleaved matching filtering method suitable for specific integrated circuit design
  • An interleaved matching filtering method suitable for specific integrated circuit design

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Embodiment 1

[0029] An interleaved matched filtering method suitable for ASIC design disclosed in this embodiment is used in a direct sequence spread spectrum system, and the spread spectrum ratio of the system is 1024.

[0030] figure 1 Shown is a schematic diagram of an interleaved matched filter structure suitable for ASIC design in a specific embodiment,

[0031] figure 2 Shown is the flow chart of the interleaved matched filtering method suitable for ASIC design in the specific implementation mode. A kind of interleaved matched filtering method suitable for application-specific integrated circuit design disclosed in this embodiment, the specific implementation steps are as follows:

[0032] Step 1. Write the 1024-bit PN code into the 1024-bit register R, count the total number of "1" in the PN code sequence as 512, and perform 2 times chip rate oversampling on the 1024 times spread spectrum signal.

[0033] Step 2, performing multi-stage delay on the spread spectrum signal.

[003...

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Abstract

The invention discloses an interleaved matching filtering method suitable for specific integrated circuit design, and belongs to the technical field of application specific integrated circuits. At first, that delay unit is used to delay the spread spectrum oversampling signal; Then, the delayed data is judged and processed, and the delayed signal is directly output or inverted according to the value of the corresponding position of the PN code, and the inverted operation is accomplished by the way of bit-by-bit inverted compensation. Finally, the pipeline adder tree is used to add and registerthe judged data step by step, and the result of the last addition plus the compensation value is the output result of the odd-even interleaved matched filter. The invention has the following advantages: (1) the design structure of the digitally matched filter can be simplified; (2) the logic sequence is optimized and logic resources are saved; (3) the timing path is shortened to meet the higher timing requirements; (4) The output result is still the sequential matched filter result of each sampling value, so it is easy to process the subsequent signal.

Description

technical field [0001] The invention relates to an interleaved matching filter method suitable for the design of special integrated circuits, which belongs to the technical field of special integrated circuits. Background technique [0002] Application Specific Integrated Circuit (ASIC) is an integrated circuit designed for a specific purpose. In the design of a dedicated spread spectrum baseband signal processing chip, the acquisition of code phase and despreading demodulation all depend on the output of digital matched filter. ASIC design cost is closely related to logic resource consumption, so logic resource consumption of digital matched filter is a key indicator in ASIC design. [0003] For N times chip rate oversampled signals, if N times full pipeline structure and parallel multiplication and addition method are used to complete matched filtering, it will cause N times increase in logic resources, which is unacceptable in ASIC design. However, the interleaved matche...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/3312G06F30/39
Inventor 王长红高飞杨烜赫孟恩同岳平越张昊星陈超凡张鹏
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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