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Semiconductor memory device

A storage device, semiconductor technology, applied in the direction of information storage, static memory, read-only memory, etc., can solve the problem of entering adjacent bit lines, etc.

Active Publication Date: 2019-03-05
株式会社PANGEA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, when the parasitic capacitance between bit lines increases or noise enters a bit line, the noise may also enter adjacent bit lines

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0016] figure 1 It is a block diagram showing a configuration example of the semiconductor memory device according to the first embodiment. The semiconductor storage device 1 can be, for example, a volatile memory such as DRAM (Dynamic Random Access Memory, dynamic random access memory), a NAND (Not AND, and not) type EEPROM (Electrically Erasable and Programmable Read-Only-Memory, electrically erasable Programmable read-only memory), ReRAM (Resistive RAM, resistive random access memory), MRAM (Magnetoresistive RAM, magnetoresistive random access memory) and other non-volatile memories. In addition, the semiconductor memory device 1 may be, for example, one memory chip, or may be a module such as a DIMM (Dual Inline Memory Module, Dual Inline Memory Module) including a plurality of memory chips.

[0017] figure 1 The shown semiconductor memory device 1 is configured as, for example, one memory chip. Hereinafter, the semiconductor memory device 1 is referred to as a memory c...

no. 2 Embodiment approach

[0066] Figure 5 It is a block diagram showing a more detailed configuration example of the bank BNK, the column decoder CD, and the row decoder RD in the second embodiment.

[0067]In the first embodiment, the capacitive element CAP is connected between the first node N1 and the second node N2. On the other hand, in the second embodiment, the capacitive element CAP is connected between the third node N3 and the fourth node N4. The third node N3 may be at any position on the connection wiring between the selection BL voltage generating circuit GEN_BL_sel as the first power supply circuit and the multiplexer MUX_BL0 as the first decoder. The fourth node N4 may be any position on the connecting wiring between the unselected WL voltage generating circuit GEN_WL_unsel as the fourth power supply circuit and the multiplexer MUX_WL0 as the second decoder. Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. In a...

no. 3 Embodiment approach

[0074] Figure 7 It is a block diagram showing a configuration example of a memory chip according to the third embodiment. The memory chip 1 further includes a noise generating unit 100 connected to an unselected BL voltage generating circuit GEN_BL_unsel as a second power supply voltage, and applies a noise voltage to an unselected bit line BL_unsel. Other configurations of the third embodiment may be the same as the corresponding configurations of the first embodiment.

[0075] The test is performed at the stage where the processing of the semiconductor wafer (preliminary step) is completed, and the noise generating unit 100 is used in this test. In the experiment, the noise generating unit 100 applied noise to the unselected bit line BL_unsel or the unselected word line WL_unsel.

[0076] For example, when the capacitive element CAP is provided between the first node N1 and the second node N2 as in the first embodiment, the noise generator 100 applies noise to the unselec...

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Abstract

A semiconductor memory device includes a memory cell array with bit lines and word lines connected thereto. A first power supply circuit generates a selected bit line voltage. A second power supply circuit generates a non-selected bit line voltage. A third power supply circuit generates a selected word line voltage. A fourth power supply circuit generates a non-selected word line voltage. A firstdecoder connects the selected bit line to the first power supply circuit and connects the non-selected bit line to the second power supply circuit. A second decoder connects the selected word line tothe third power supply circuit and connects the non-selected word line to the fourth power supply circuit. A capacitive element is between a first node that is between the second power supply circuitand the first decoder and a second node that is between the third power supply circuit and the second decoder.

Description

[0001] [Related Application] [0002] This application enjoys the priority of Japanese Patent Application No. 2017-164763 (filing date: August 29, 2017) as the basic application. This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention relate to a semiconductor memory device. Background technique [0004] In recent years, with the miniaturization of semiconductor memory devices, the interval between adjacent bit lines or word lines has become extremely narrow. When the interval between bit lines or word lines is narrowed, the parasitic capacitance between adjacent bit lines or the parasitic capacitance between adjacent word lines becomes larger. For example, when the parasitic capacitance between bit lines increases or noise enters a bit line, the noise may also enter adjacent bit lines. Contents of the invention [0005] Embodiments provide a semicondu...

Claims

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Application Information

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IPC IPC(8): G11C7/12G11C7/10G11C5/02
CPCG11C5/02G11C7/1039G11C7/12G11C5/063G11C7/02G11C8/14G11C5/147G11C8/08G11C8/10G11C16/30
Inventor 杉本刚士宫崎隆行犬塚雄贵
Owner 株式会社PANGEA
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