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Semiconductor device and manufacturing method thereof

A semiconductor and conductive type technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as reducing on-resistance, and achieve the effect of improving latch-up damage tolerance

Active Publication Date: 2021-09-28
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, for example, in the technique of Patent Document 2, the on-resistance is reduced by forming a current suppressing layer

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0056] image 3 is a cross-sectional view showing the structure of the semiconductor device 51 according to the first embodiment. This semiconductor device 51 is a planar gate type SiC-IGBT using silicon carbide (SiC) as a semiconductor material. In addition, since silicon carbide is used as a semiconductor material, the semiconductor device 51 can operate stably even at high temperatures.

[0057] The semiconductor device 51 includes: a collector electrode 1; a collector region 2 of the first conductivity type; a drift region 3 of the second conductivity type; a buried region 4 of the first conductivity type; and a carrier trap region 5 of the second conductivity type. ; The carrier accumulation region 6 of the second conductivity type; The base region 7 of the first conductivity type; The emitter region 8 of the second conductivity type; The base contact region 9 of the first conductivity type; The gate electrode 10; an electrode oxide film 11; and an emitter electrode 12....

Embodiment approach 2

[0087] A semiconductor device according to Embodiment 2 of the present invention will be described as in Embodiment 1, taking a planar gate type SiC-IGBT using silicon carbide (SiC) as a semiconductor material as an example. Figure 11 It is a cross-sectional view showing the structure of the semiconductor device 52 according to the second embodiment. In the semiconductor device 52 according to the second embodiment, the image 3 In the semiconductor device 51 of , the carrier storage region 6 is not arranged under the base contact region 9 , and the carrier trap region 5 is connected to the base region 7 .

[0088] According to the semiconductor device 52 described in Embodiment 2, during the off operation of the SiC-IGBT, holes as minority carriers accumulated in the drift region 3 preferentially bypass the buried region 4 and reach the base contact region 9 . At this time, the holes directly reach the base region 7 without bypassing the carrier storage region 6 . Therefo...

Embodiment approach 3

[0090] A semiconductor device according to Embodiment 3 of the present invention will be described as in Embodiment 1, taking a planar gate type SiC-IGBT using silicon carbide (SiC) as a semiconductor material as an example. Figure 12 It is a cross-sectional view showing the structure of the semiconductor device 53 according to the third embodiment. In the semiconductor device 53 according to Embodiment 3, compared to the semiconductor devices 51 and 52 shown in Embodiments 1 and 2 above, the carrier trap region 5a has the first conductivity type instead of the second conductivity type. conductivity type. That is, the carrier trap region 5 a of the first conductivity type is disposed between the buried region 4 and the base region 7 . In addition, the impurity concentration of the first conductivity type in the carrier trapping region 5a is expected to be 1×10 15 cm -3 ~1×10 21 cm -3 In the range.

[0091] According to the semiconductor device 53 described in Embodiment...

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Abstract

The object is to provide a technique capable of improving the breakdown resistance of the latch. A semiconductor device includes an emitter region, a base contact region, a buried region, and a carrier trapping region. The emitter region and the base contact region are selectively arranged on the upper surface of the base region in a state of being adjacent to each other. The buried region is disposed in the drift region below the base contact region or the emitter region. The carrier trapping region is arranged between the buried region and the base region, and the carrier lifetime is lower than that of the drift region.

Description

technical field [0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background technique [0002] An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: hereinafter referred to as “IGBT”) using silicon (Si) or silicon carbide (SiC) as a semiconductor material is known. [0003] In IGBTs, various techniques have been proposed in order to reduce the resistance at the time of conduction, that is, the on-resistance. For example, in the technology of Patent Document 1, on-resistance is reduced by forming a carrier storage region for carrier storage. In addition, for example, in the technique of Patent Document 2, the on-resistance is reduced by forming a current suppressing layer. [0004] Patent Document 1: Japanese Patent Laid-Open No. 2005-347289 [0005] Patent Document 2: Japanese Patent Laid-Open No. 2008-211178 Contents of the invention [0006] The problem to be solved by the inven...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/12H01L29/739H01L29/78
CPCH01L29/7395H01L29/1608H01L29/083H01L29/0696H01L29/36H01L29/66333H01L29/12H01L29/78H01L29/739H01L21/046H01L29/063H01L29/1095H01L29/66068H01L29/7393
Inventor 滨田宪治小西和也海老原洪平
Owner MITSUBISHI ELECTRIC CORP
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