30results about How to "Increase damage tolerance" patented technology

Lightweight structural component including at least one panel and at least one stiffening element oriented one of lengthwise and crosswise. The at least one stiffening element includes two side pieces. Each of the two side pieces is at least partially connected to the panel in a material-locking manner. The two side pieces are connected to the panel at two separate joint zones. A method of producing the lightweight structural component includes milling the at least one panel to form at least one thickened region and joining the two side pieces to the at least one panel at the two separate joint zones. This Abstract is not intended to define the invention disclosed in the specification, nor intended to limit the scope of the invention in any way.

A semiconductor device having a high withstand voltage is provided. An activation groove (22a) is composed of a long and narrow main groove part (26) and a sub-groove part (27) which is connected with a side plane in a longitudinal direction of the main groove part. On a bottom plane of the main groove part (26), a second conductivity type embedding region (24) having a height lower than a bottom plane of a second conductivity type base diffusion region (32a) is arranged, and in the sub-groove part (27), a second conductivity type activation groove filling region (25) contacting the base diffusion region (32a) is arranged. The embedding region (24) is brought into contact with the base diffusion region (32a) through the activation groove filling region (25). In the one activation groove (22a), since one gate groove (83) is formed at a part upper than the embedding region (24), a gate electrode plug (48) is not interrupted and an electrode pattern is simplified.

The invention provides a semiconductor device which can enhance the breakdown resistance during the recovery operation. The semiconductor device (100) includes an insulated gate bipolar transistor region (1) and a diode region (2) adjacent to each other, wherein the insulated gate bipolar transistor region (1) includes base layers (9) of a second conductive type provided on the first main surface side, emitter layers (8) of the first conductive type selectively provided in a surface layer of the base layer (9) on the first main surface side, multiple gate electrodes (7a) provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer (8), the base layer (9), and the drift layer (12) via a gate insulating film (6a), carrier injection suppression layers (10) of the first conductive type selectively provided in a surface layer of the base layer (9) on the first main surface side and sandwiched by the base layers (9) in the first direction.

The invention provides a semiconductor device which can improve the breakdown tolerance during recovery operation. The semiconductor device according to the present application includes: a semiconductor substrate including a first main surface and a second main surface; a hole injection region including a hole injection layer of a second conductivity type and a semiconductor layer of a second conductivity type provided on the second main surface side; a diode region including: an anode layer of a second conductivity type provided on the first main surface side and a cathode of a first conductivity type on the second main surface side, the diode region having no semiconductor layer of a first conductivity type between the second main surface side end portion of the anode layer and the first main surface of the anode layer; a boundary region including: a boundary portion semiconductor layer of a second conductivity type provided on the first main surface side, a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer, and the semiconductor layer of a second conductivity type provided to protrude from the hole injection region on the second main surface side, which are arranged between the diode region and the hole injection region.

The invention relates to a method for manufacturing flat, single or double curved core composites 1, 23 with at least one folded honeycomb core 4, 19. Prior to applying the initially not yet hardened cover layers 2, 3, 13, 22 a curable and later removable core filler material 15, 16 is introduced into full-length drainage-enabling channels 5, 6 of the folded honeycomb core 4, 19 in order to prevent telegraphing of the cover layers 2, 3, 13, 22 into the channels 5, 6 of the folded honeycomb core when arranging and / or hardening the cover layers 2, 3, 13, 22 and to produce edge-free and polygon-free surfaces of the core composite 1, 23. The core composites 1, 23 made according to the method have optimum structural mechanical properties, an ideal surface quality from the aerodynamic and aesthetic point of view, whereby a direct reprocessing of the core composites 1, 23 is possible without the need for further time and cost-intensive as well as in some circumstances weight-increasing finishing steps. With the method it is possible to manufacture in particular one-piece fuselage sections with wound core composites 1, 23 with a folded honeycomb 4, 19 as well as shell segments with laid cover layers 2, 3, 13, 22 for longitudinally divided (segmented) fuselage sections for large aircraft.

Provided is a semiconductor device having improved breakdown tolerance during a recovery operation. An insulated gate bipolar transistor region (1) of a semiconductor device (100) is arranged in parallel with a diode region (2) in a first direction along a first main surface of a semiconductor substrate, and has: a second conductivity type base layer (9) provided on a surface layer on the first main surface side of the semiconductor substrate; an emitter layer (8) of a first conductivity type, which is selectively provided on a surface layer on the first main surface side of the base layer (9), and which has a higher impurity concentration than the drift layer; a plurality of gate electrodes (7a) arranged in parallel in the first direction and facing the emitter layer, the base layer, and the drift layer with a gate insulating film (6a) therebetween; a counter-doped layer (10) provided on the surface layer of the base layer and having a second conductivity type impurity concentration higher than that of the base layer and a first conductivity type impurity concentration higher than that of the drift layer; and a collector layer of a second conductivity type provided on a surface layer on the second main surface side of the semiconductor substrate.

The invention provides a thermoplastic wave-absorbing material and a preparation method thereof. The thermoplastic wave-absorbing material comprises: reinforced fiber cloth; and a thermoplastic wave-absorbing film, which is located on the upper and lower sides of the reinforced fiber cloth. The thermoplastic wave-absorbing material of the present invention uses a thermoplastic resin with a linear molecular structure as an adhesive matrix material, has good toughness, and can greatly improve the impact resistance and damage tolerance of the thermoplastic wave-absorbing material, and the thermoplastic wave-absorbing material also has It can be processed and shaped many times, and can also be recycled, which is beneficial to protect the environment and save resources; compared with the existing thermosetting absorbing materials, the thermoplastic absorbing materials only need to be stored at room temperature, and the storage period is not as long as limit.

According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.

The invention relates to an injection mould for improving a pouring gate and a manufacturing method of the injection mould, and the mould is provided with a detachable pouring core part. The injection mould comprises the pouring core part which is independent of the injection mould, the pouring core part forms the pouring gate and a pouring channel, the pouring core part and the whole mould can be conveniently separated, when the pouring core part is abraded during the working process and plastic molding is further influenced, the pouring core part can be detached from the mould for replacement, thereby being time-saving and labor-saving during actual applications.

A method for preparing a graphene network toughened ZrC-SiC ultra-high temperature ceramic material, and the invention relates to the field of preparation methods of ceramic materials. The present invention aims to solve the technical problem of the existing poor ZrC-SiC damage tolerance. Method: 1. Preparation of graphene oxide aqueous solution; 2. Preparation of graphene oxide dispersion; 3. Directional freezing to prepare PVA-modified graphene network; 4. Thermal reduction and vacuum impregnation to prepare graphene network-wrapped ceramic powder Green body; 5. Spark plasma sintering. The fracture toughness of the ceramic material prepared by the inventive method is by 3.82MPa m 1 / 2 increased to 4.26MPa·m 1 / 2 , the critical crack size increased from 26.8μm to 119.4μm, and the work of fracture increased from 44.7J / m 2 increased to 151.6J / m 2 . The invention is used for preparing ceramic materials.