Copper-filled groove structure and method of manufacturing the same

Abstract

The invention discloses a copper filled groove structure. The copper filled groove structure includes a groove formed in a first dielectric layer; a barrier layer is formed on the bottom surface and side surfaces of the groove; a first seed crystal layer of pure copper is formed on the surface of the barrier layer; a second seed crystal layer of a copper alloy is formed on a surface of the first seed crystal layer at the top of the side of the groove; a copper body layer completely fills the groove and forms a groove structure; the bottom surface and the side surface bottom of the copper bodylayer are in direct contact with the first seed crystal layer to reduce the parasitic resistance of the groove structure; and the top of the side of the copper body layer is in direct contact with thesecond seed crystal layer, and the electromigration of the groove structure is reduced through the copper alloy material of the second seed crystal layer. The invention discloses a method for manufacturing the copper filled groove structure. The invention can improve the EM performance of the device, and can reduce the parasitic resistance of the device; and the invention is particularly suitablefor application in copper through-holes below 20 nm.

Description

technical field [0001] The invention relates to the manufacturing field of semiconductor integrated circuits, in particular to a copper-filled groove structure. The invention also relates to a method of manufacturing a copper-filled groove structure. Background technique [0002] As the size of metal copper wires shrinks, metal electromigration (ElectroMigration, EM) becomes more challenging. When the process node reaches 28nm, the industry adopts copper alloy (Cu alloy) seed crystal (seed) to improve EM performance. This method has no impact on the process flow, that is, it only needs to replace the copper seed crystal with copper alloy seed crystal. The copper alloy seed crystal will increase the resistance of the copper wire. For example, in the via hole, the via hole is used to connect the upper and lower metal layers. The copper alloy seed layer is formed, and the main body layer of copper is usually realized by electroplating (plating) process. After the electroplati...

AI Technical Summary

Problems solved by technology

When the process node reaches 28nm, the industry adopts copper alloy (Cu alloy) seed crystal (seed) to improve EM performance. This method has no impact on the process flow, that is, it only needs to replace the copper seed crystal with copper alloy seed crystal. The copper alloy seed crystal will increase the resistance of the copper wire. For example, in the via hole, the via hole is used to connect the upper and lower metal layers. The copper alloy seed layer is formed, and the main body layer of copper is usually realized by electroplating (plating) process. After the electroplating process of the main body layer of copper is completed, the chemical mechanical polishing (CMP) process of copper is usually required to remove the metal layer outside the groove, such as copper The main layer and the copper alloy seed layer at the bottom are removed; in this way, the copper main layer cannot directly contact the bottom metal layer, but it contacts the bottom metal layer through the copper alloy seed layer, which will increase the parasitic of the via Resistance is Rc

[0003] When the process node of the semiconductor integrated circuit is below 20nm, in order to reduce the parasitic resistance of the metal interconnection, it is necessary to reduce the parasitic resistance of the through hole in the metal interconnection, so that the copper alloy seed layer in the through hole needs to use the copper seed crystal again layer; since the copper seed layer is used, selective cobalt (Co) growth is required to improve EM after the copper body layer is formed and CMP is performed, which will obviously increase the complexity of the process and increase the process cost

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