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Semiconductor wafer lapping method and semiconductor wafer

A grinding method and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, grinding machine tools, etc., can solve problems such as deterioration of nanometer topography

Active Publication Date: 2019-04-16
SUMCO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is considered that the nano-morphology of semiconductor wafers may be deteriorated due to fluctuations caused by the above-mentioned slicing process, grinding process, and double-end grinding process.

Method used

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  • Semiconductor wafer lapping method and semiconductor wafer
  • Semiconductor wafer lapping method and semiconductor wafer
  • Semiconductor wafer lapping method and semiconductor wafer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0063] Next, in order to clarify the effects of the present invention, the following examples are given, but the present invention is not limited by the following examples.

[0064] (Invention Example 1)

[0065] According to the aforementioned figure 1 structure and Figure 5 In the flowchart shown, the grinding of a silicon wafer with a diameter of 450 mm was carried out. That is, a silicon wafer with a diameter of 450 mm obtained by slicing a single crystal ingot was loaded on a carrier plate and placed between the upper stage and the lower stage of the polishing apparatus. In addition, the total grinding time until the target grinding allowance was obtained was confirmed in advance.

[0066] First, the grinding of the silicon wafer was started and stopped after 35% of the total grinding time had elapsed. After stopping the grinding, use the adsorption pad to remove the silicon wafer from the carrier plate, turn over the silicon wafer opposite to the upper platform and ...

example 1

[0070] A silicon wafer with a diameter of 450 mm was polished in the same manner as Inventive Example 1 except that the polishing was not stopped and the polishing was terminated after the total polishing time had elapsed. That is, in Conventional Example 1, inversion of the silicon wafer and restart of polishing were not performed.

[0071]

[0072] Alkali etching (hereinafter abbreviated as "alkali ET") was performed on the polished silicon wafers of Invention Examples 1 to 5 and Conventional Example 1 under the same conditions. Then, using a capacitive shape measuring device (manufactured by Kobelco Scientific Research Co., Ltd.; SBW-451 / R), the radial direction of the silicon wafer (the direction of the arrow shown in the nano-topography diagram, which corresponds to the cross-sectional view of the wire saw moving direction) was measured. , so as not to be affected by the ups and downs of slice cutting), the graph of the shape distribution. show the result in Image 6 ...

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Abstract

Provided is a semiconductor wafer lapping method with which the occurrence of a ring-shaped pattern in a nanotopography map can be suppressed. The semiconductor wafer lapping method according to the present invention is characterized by comprising: a stopping step of stopping lapping of a semiconductor wafer W; an inverting step, after the stopping step, of inverting opposing surfaces of the semiconductor wafer W with respect to an upper surface plate 10A and a lower surface plate 10B; and a resuming step, after the inverting step, of resuming the lapping of the semiconductor wafer W while theinversion of the opposing surfaces Wa, Wb is maintained.

Description

technical field [0001] The invention relates to a grinding method of a semiconductor wafer and the semiconductor wafer. Background technique [0002] Compound semiconductor wafers such as silicon wafers and GaAs are known as semiconductor wafers. In general, semiconductor wafers are obtained by sequentially going through the following steps: a slicing process in which a single crystal ingot is sliced ​​with a wire saw to obtain a thin disc-shaped wafer; a grinding process in which the front and back surfaces of the sliced ​​wafer are flattened and made Thickness; and polishing process, eliminate the surface unevenness of the wafer after grinding, and implement high flatness mirror surface processing. In addition, a double-end grinding process as mechanical grinding may be performed instead of the grinding process or together with the grinding process. [0003] In recent years, especially in large-diameter semiconductor wafers, "nanotopography" (SEMI standard M43), which is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/304B24B37/08
CPCB24B37/08H01L21/304B24B37/042H01L21/02013H01L21/02024H01L21/02381B24B37/28H01L29/16H01L29/34
Inventor 桥本大辅又川敏桥井友裕
Owner SUMCO CORP
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