Programmable super-speed advanced setting type frequency divider

A frequency divider, ultra-high-speed technology, applied in the direction of electrical components, automatic power control, logic circuits with logic functions, etc., can solve the problems of reducing the performance of frequency dividers, large area costs, and large delays, etc., to achieve Ultra-high-speed frequency division, low area overhead, and strong reusability

Pending Publication Date: 2019-04-23
南京胜跃新材料科技有限公司
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The programmable frequency divider is a frequency divider with a variable frequency division ratio. The advantages of the traditional programmable frequency divider are regular structure, convenient layout and fast speed. Howe

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Programmable super-speed advanced setting type frequency divider
  • Programmable super-speed advanced setting type frequency divider
  • Programmable super-speed advanced setting type frequency divider

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0034] Example

[0035] The programmable ultra-high-speed ultra-pre-digital frequency divider of this embodiment is such as figure 1 As shown, it includes a NOR gate 107, a NAND gate 108, a NOR gate 109, a 0th bit frequency divider module 103, a 1st bit frequency divider module 104, a 2nd bit frequency divider module 105 and N third bit frequency dividers Module 106, N is a positive integer greater than or equal to 1;

[0036] The input terminal CK of the programmable ultra-high-speed super-pre-digital frequency divider is connected to the input terminal CK of the zeroth frequency divider module 103 through the first inverter 101 and the second inverter 102 connected in series, the first inverter The connection node with the second inverter is connected to the input terminal CN of the 0th digit frequency divider module 103; the output terminal OUT of the 0th digit frequency divider module 103 constitutes the output terminal of the programmable ultra-high-speed super pre-digital fr...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a programmable super-speed advanced setting type frequency divider. The programmable super-speed advanced setting type frequency divider comprises a first NOR gate, a first NAND gate, a second NOR gate, a 0-th bit frequency division module, the first bit frequency division module and N third bit frequency division modules. Through the programmable super-speed advanced setting type frequency divider disclosed by the invention, the circuit structure is simple, a full-digital circuit design is adopted, the reusability is strong, the area overhead is low, and the scale iseasy to extend; 2 to 2N frequency division values can be realized in a programmable way, and the programming range is extensive; the setting is performed by adopting a method of quickly presetting internal latch node states of various frequency-division modules, a register setup problem caused by over-high input clock frequency is avoided, and the super-speed frequency division can be realized.

Description

technical field [0001] The invention relates to a programmable ultra-high-speed super-predigital frequency divider, which belongs to the technical field of integrated circuits. Background technique [0002] The frequency divider is located between the Voltage Controlled Oscillator (VCO) and the Phase Frequency Detector (PFD) in the Phase Locked Loop (PLL), and its function is to reduce the VCO output signal frequency , and feed it back to the PFD for phase and frequency comparison with the reference signal. [0003] Figure 7 Shown is the 8 / 9 dual-mode frequency divider realized by the design method of asynchronous logic circuit. When the frequency-division ratio control MC signal is at low level, the detector circuit stops working to realize 8-frequency division; when the output signals of MC and each frequency divider are at high level, the detector generates a negative pulse, and the negative pulse The pulses "swallow" one cycle of the clock signal, achieving a divide b...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03L7/18H03K19/20
CPCH03K19/20H03L7/18Y02D30/70
Inventor 孙嘉斌贾一平刘雨婷周丽萍陈倩胡凯孙晓哲
Owner 南京胜跃新材料科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products