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Array substrate, preparation method thereof, and display panel

An array substrate and substrate technology, which is applied to semiconductor/solid-state device parts, instruments, semiconductor devices, etc., can solve the problems of small aperture ratio and low yield rate, and achieve increased aperture ratio, improved yield rate, and good process compatibility Effect

Active Publication Date: 2019-05-14
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the embodiments of the present invention is to provide an array substrate and its preparation method, and a display panel, so as to solve the defects of the existing structure with a small opening ratio and a low yield rate.

Method used

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  • Array substrate, preparation method thereof, and display panel
  • Array substrate, preparation method thereof, and display panel
  • Array substrate, preparation method thereof, and display panel

Examples

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no. 1 example

[0057] Figure 5 is a schematic structural diagram of the first embodiment of the array substrate of the present invention, Figure 6 for Figure 5 The cross-sectional view of A-A in the middle. Such as Figure 5 and Figure 6 As shown, the array substrate provided in this embodiment includes:

[0058] base 10;

[0059] A pixel electrode 50, a gate line 30 and a gate electrode 11 arranged on the substrate 10;

[0060] a gate insulating layer 12 covering the pixel electrode 50, the gate line 30 and the gate electrode 11;

[0061] The active layer 13, the source electrode 14, the drain electrode 15 and the data line 40 arranged on the gate insulating layer 12, a conductive channel is formed between the source electrode 14 and the drain electrode 15;

[0062] A passivation layer 16 covering the active layer 13, the source electrode 14, the drain electrode 15 and the data line 40, and a transfer via hole is opened on the passivation layer 16 to simultaneously expose the dra...

no. 2 example

[0073] Figure 13 It is a schematic diagram of the structure of the transfer via according to the embodiment of the present invention. Such as Figure 13 As shown, the transfer via hole is actually composed of half of the shallow hole (overlapping the drain electrode 15 ) and half of the deep hole (overlapping the pixel electrode 50 ), which is also called a half via (Half Via) design. Since the active layer and the source electrode / drain electrode are formed by a patterning process using a half-tone or gray-tone mask, there is a semiconductor film under the drain electrode 15, and the line width CD of the semiconductor film is greater than that of the drain electrode 15. The line width CD means that the active layer protrusion 131 exists. The active layer protrusions 131 appear because the wet etching method is used for the metal thin film, and the dry etching method is used for the semiconductor thin film, so the ends of the two cannot be guaranteed to be flush, resulting ...

no. 3 example

[0078] Figure 15 It is a schematic structural diagram of the third embodiment of the array substrate of the present invention. This embodiment is an extension of the aforementioned first embodiment. The main structure of the array substrate in this embodiment is the same as that of the aforementioned first embodiment. compensation block and a second compensation block. Such as Figure 15 As shown, in this embodiment, the first compensation block 60A is arranged on the side of the connection electrode 60 adjacent to the grid line 30, and the second compensation block 60B is arranged on the side of the connection electrode 60 away from the grid line 30, that is, both sides of the connection electrode 60 are Compensation blocks are provided. The structure of the first compensation block 60A is the same as that of the aforementioned second embodiment, and will not be repeated here. In the direction parallel to the data line 40, the orthographic projection of the second compen...

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Abstract

The embodiment of the invention provides an array substrate, a preparation method thereof, and a display panel. The array substrate comprises a base, a pixel electrode, a film transistor, a passivation layer and a connecting electrode, wherein the pixel electrode and the film transistor are arranged on the base; the passivation layer covers the film transistor and is provided with a through connection through hole which simultaneously exposes the pixel electrode and the drain electrode of the film transistor; and the connecting electrode is arranged on the passivation layer and is simultaneously connected with the pixel electrode and the drain electrode through the through connection through hole. By use of the array substrate, through one through connection through hole, connection between the drain electrode and the pixel electrode is realized, the amount of through holes is effectively reduced, the aperture ratio of the display panel is increased, the quality of a product is improved, and a yield is improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel. Background technique [0002] Liquid Crystal Display (LCD) has the characteristics of small size, low power consumption, and no radiation, and has been developed rapidly in recent years. The main structure of the LCD includes a thin film transistor array (Thin Film Transistor, TFT) substrate and a color filter (Color Filter, CF) substrate of the cell (CELL), and liquid crystal (Liquid Crystal, LC) molecules are filled between the array substrate and the color filter substrate , by controlling the common electrode and the pixel electrode to form an electric field that drives the deflection of the liquid crystal to achieve grayscale display. According to the display mode, LCD can be divided into: Twisted Nematic (TN) display mode, In Plane Switching (IPS) display mode, Advanced SuperDimension Switch (ADS) disp...

Claims

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Application Information

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IPC IPC(8): G02F1/1362
CPCH01L23/528H01L23/485H01L27/124H01L27/1248G02F1/134372G02F1/136227G02F1/134363G02F1/13439G02F1/1368G02F2201/40H01L27/1259
Inventor 王小元王武方琰吴胜学
Owner BOE TECH GRP CO LTD
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