Packaging structure and packaging method of chip module and wafer level chip

Abstract

The invention provides a chip module, a wafer-level chip packaging structure and a packaging method. The packaging structure forms metal bumps above the pads of two adjacent chip units. Since the size of the metal bumps is larger than the size of the pads , the thickness is thicker, which increases the effective contact area between the follow-up circuit in the chip unit and the conductive wiring layer, and improves the conductive reliability of the chip packaging structure; one of the technical solutions of the present invention is to directly emboss the optical element on the surface of the wafer The device simplifies two processes into one process, shortens the packaging process, and reduces production costs; the first opening is formed by cutting from the non-functional surface of the wafer to the metal bump direction, which is suitable for wafers that are not suitable for laser drilling Material; and a pre-cutting step is set before the cutting step, so that only the embossed components need to be cut during the cutting step, which reduces the problems of edge material delamination, product slivers, broken knives, and edge collapse during the cutting process.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip module, a wafer-level chip packaging structure and a packaging method. Background technique [0002] The wafer-level chip packaging process based on TSV (Through Silicon Via) technology is to make holes on the non-functional surface of the wafer substrate. The opening extends from the non-functional surface of the wafer to the functional surface of the wafer, and exposes Welding pads on the functional surface, laying metal lines on the inner wall of the opening, leading the electrical properties of the pads to the non-functional surface of the wafer, after preparing bumps on the non-functional surface, cutting to form a single chip packaging structure. Among them, through-hole processing on the wafer is the core of TSV technology. There are two main types, one is deep reactive ion etching, and the other is laser drilling; deep reactive ion etching technolog...

AI Technical Summary

Problems solved by technology

Among them, through-hole processing on the wafer is the core of TSV technology. There are two main types, one is deep reactive ion etching, and the other is laser drilling; deep reactive ion etching technology must rely on thick film lithography technology , pre-formed through-hole patterns on the wafer surface, the cost is high; laser drilling technology cannot meet the production of through-holes with smaller aperture (<10μm) and high aspect ratio

Because some wafers such as VCSEL wafers are not suitable for laser drilling, and the pads in the wafer are small in size and thin in thickness, the effective contact area of ​​the circuit is very limited, which affects the reliability of the product's electrical conductivity.

Moreover, there are too many types of materials located at the cutting line, and problems such as edge material delamination, product splits, and cutting edge chipping may occur

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