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LDMOS device and preparation method thereof

A device and semiconductor technology, which is applied in the field of LDMOS devices and its preparation, can solve the problems of affecting the distribution of the electric field on the surface of the device, affecting the working voltage of the device, increasing the on-resistance, etc., to optimize the distribution of the surface electric field, eliminate the peak value of the electric field, and improve the reflection rate. The effect on the breakdown voltage

Active Publication Date: 2019-08-13
NANJING UNIV OF POSTS & TELECOMM +1
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The P-type PN variable-doping field-reducing layer B13 is located in the N-type epitaxial layer B3. The P-type PN variable-doping field-reducing layer B13 can reduce the on-resistance of the LDMOS device to a certain extent, but due to the distribution of the surface electric field It can be seen that there will be an electric field trough at the forward biased PN junction, which will affect the electric field distribution on the surface of the device.
In addition, in order to optimize the surface electric field distribution, the PN variable doping field drop layer B13 should be as close as possible to the P-type semiconductor body region B4. The current channel between the two decreases as the distance between the two decreases, so it will cause Increase the on-resistance, these shortcomings seriously affect the further improvement of the device's operating voltage

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  • LDMOS device and preparation method thereof
  • LDMOS device and preparation method thereof
  • LDMOS device and preparation method thereof

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Embodiment 1

[0040] This embodiment proposes an LDMOS with variable doping PN variable doping field drop layer, image 3 A cross-sectional schematic diagram of an LDMOS device provided for Embodiment 1 of the present invention, such as image 3 As shown, it includes a semiconductor substrate 1 located at the bottom; a buried layer 2 on a p-type substrate; an epitaxial layer 3 located above the buried layer; the epitaxial layer 3 includes a variable doped PN variable doping drop field layer 16. The left half 16-1 of the PN variable doping drop field layer is a P-type variable doping region, and the concentration decreases linearly from left to right to 0cm -3 , the right half part 16-2 of the PN variable-doped drop field layer is an N-type doped region, and the concentration decreases linearly from right to left to 0cm -3 .

[0041] The PN variable doping drop field layer 16 is connected to the P-type semiconductor body region 4 and the N-type semiconductor drain region 5; the P-type semi...

Embodiment 2

[0044] Others are the same as in Embodiment 1, the difference is that the P-type impurity concentration of the P-type variable doping region 16-1 in the PN variable-doping drop-off layer 16 is a Gaussian distribution that decreases from left to right, and the N-type variable doping The N-type impurity concentration distribution of the impurity region 16-2 is a Gaussian distribution that decreases from right to left, such as Figure 4 shown.

[0045] In addition, the present invention also makes some improvements on the basis of the traditional LDMOS device preparation process to optimize the breakdown voltage and on-resistance of the device. The main process such as Figure 5 shown. The main improvement includes forming the PN variable doping drop field layer 16 in the epitaxial layer 3 through two window ion implantations, and making the gate 14 in the lateral trench 17, so that the PN variable doping drop field layer 16 and the The N-type semiconductor drain region 5 on o...

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Abstract

The invention provides an LDMOS device, and the device comprises a semiconductor substrate, a buried layer, an epitaxial layer, a source metal, drain metal and a field oxide layer. A PN variable doping field reduction layer, a P-type semiconductor body region and an N-type semiconductor drain region are arranged on the epitaxial layer, wherein the left half part of the PN variable doping field reduction layer is a P-type variable doping region, and the right half part of the PN variable doping field reduction layer is an N-type variable doping region. The concentration of P-type impurities inthe P-type variable doping region is gradually decreased to 0 cm<-3> from left to right. The concentration of N-type impurities in the N-type variable doping region is gradually decreased to 0 cm<-3>from right to left. A PN variable doping field reduction layer is prepared in an epitaxial layer, so the uniform electric field distribution is generated in the middle of a drift region. Meanwhile, ahigh electric field peak value at a main junction is eliminated, the surface electric field distribution of the drift region is optimized, and therefore the reverse breakdown voltage of the device canbe improved; in addition, the PN variable doping field reduction layer can improve the concentration of a drift region of a conventional device, effectively improve the current capability of the device and reduce the on-resistance of the device.

Description

technical field [0001] The invention relates to an LDMOS device and a preparation method thereof, belonging to the technical field of integrated circuits. Background technique [0002] With the development of power electronics technology, power integrated circuits have put forward higher requirements on the performance of semiconductor power devices. As the core device of power integrated circuits, lateral semiconductor power devices need to provide high withstand voltage and low on-resistance . LDMOS (Laterally Diffused Metal Oxide Semiconductor Transistor) is widely used due to its good process compatibility and easy monolithic integration of the source, gate and drain distributed on the surface with low-voltage logic circuits through internal wiring. However, when the breakdown voltage of LDMOS increases, the on-resistance often increases at the same time. This contradictory relationship limits the application of this type of device in the field of high voltage and high...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L29/423H01L21/336
CPCH01L29/7823H01L29/7824H01L29/0623H01L29/7825H01L29/4236H01L29/66704
Inventor 姚佳飞张泽平郭宇锋杨可萌
Owner NANJING UNIV OF POSTS & TELECOMM